Figure 15.Master Clock Circuit - Cirrus Logic Crystal CDB4228A Manual

1
7
GND
TP1
SPDIF_MCLK
SPDIF_MCLK
DAP_MCLK
DAP_MCLK
R106
75
R4
33
GND
REFCLK_CTRL[3..0]
VCC
C3 C4
47nf 47nf
GND GND
OFF
VCC
ON
U1
14
NC +5V
C1
8
GND CLKOUT
47nf
12.2880 MHZ
GND GND
R1
OSC
TP2
33
U2A
74AC125SC
2 3
REFCLK_CTRL3
U2B
74AC125SC
5 6
REFCLK_CTRL2
U2C
74AC125SC
9 8
REFCLK_CTRL1
U2D
74AC125SC
REFCLK
11 12
REFCLK_CTRL0
Figure 15. Master Clock Circuit
3
JP1
2
1
HDR3X1
OSC
C2
47nf
OSC
SPDIF_MCLK
MUX_ MCLK
R2
33
JP2
REFCLK
2 1 REFCLK
4 3
6 5
HEADER 3X2
REFCLK SELECT
R3
0