ARM DSTREAM-ST System And Interface Design Reference Manual page 6

List of Figures
ARM DSTREAM-ST System and Interface Design
®
Reference Guide
Figure 1-1
Figure 1-2
Figure 1-3
Figure 1-4
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
Figure 2-13
Figure 2-14
Figure 2-15
Figure 2-16
Figure 2-17
Figure 2-18
ARM 100893_0100_00_en
Example reset circuit logic ..................................................................................................... 1-14
TAP Controllers serially chained within an ASIC ................................................................... 1-15
Typical JTAG connection scheme .......................................................................................... 1-17
Target interface logic levels ................................................................................................... 1-18
ARM JTAG 20 connector pinout ............................................................................................ 2-20
CoreSight 20 connector pinout .............................................................................................. 2-22
Typical SWD connections ...................................................................................................... 2-25
SWD timing diagrams ............................................................................................................ 2-26
Clock waveforms ................................................................................................................... 2-27
JTAG port timing diagram ...................................................................................................... 2-28
JTAG connection without buffers ........................................................................................... 2-30
JTAG connection with TDO buffer ......................................................................................... 2-30
Daisy-chained JTAG connection without buffers ................................................................... 2-31
Daisy-chained JTAG connection with TCK buffers ................................................................ 2-32
JTAG connection with de-skewed buffers .............................................................................. 2-33
Input ....................................................................................................................................... 2-34
Output .................................................................................................................................... 2-34
Input/Output ........................................................................................................................... 2-34
Reset output .......................................................................................................................... 2-34
Reset output with feedback ................................................................................................... 2-34
VTRef input ............................................................................................................................ 2-35
VTRef input (decoupled) ........................................................................................................ 2-35
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