ARM DSTREAM-ST System And Interface Design Reference Manual page 21

Signal I/O
TMS Output
TCK Output
RTCK Input
nTRST Output
nSRST Input/
Output
DBGRQ Output
DBGACK Input
SWDIO (SWD Input/
mode) Output
SWCLK (SWD Output
mode)
SWO (SWD Input
mode)
VTRef Input
GND -
ARM 100893_0100_00_en
Description
The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target. TMS can
be pulled HIGH on the target to keep the TAP controller inactive when not in use.
The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically pulled
HIGH on the target.
The Return Test Clock pin echoes the test clock signal back to DSTREAM-ST for use with adaptive
mode clocking. If RTCK is generated by the target processor, you are advised to series terminate it.
RTCK can be pulled HIGH or LOW on the target when not in use.
The Test Reset pin resets the TAP controller of the processor to allow debugging to take place. nTRST is
typically pulled HIGH on the target and pulled strong-LOW by DSTREAM-ST to initiate a reset. The
polarity and strength of nTRST is configurable.
The System Reset pin fully resets the target. This signal can be initiated by DSTREAM-ST or by the
target board (which is then detected by DSTREAM-ST). nSRST is typically pulled HIGH on the target
and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.
The Debug Request pin stops the target processor and puts it into debug state. DBGRQ is rarely used by
current systems and is usually pulled LOW on the target.
The Debug Acknowledge pin notifies DSTREAM-ST that a debug request has been received and the
target processor is now in debug state. DBGACK is rarely used by current systems and is usually pulled
LOW on the target.
The Serial Wire Data I/O pin sends and receives serial data to and from the target during debugging. You
are advised to series terminate SWDIO close to the target processor.
Note
SWDIO signal is bidirectional and the functionality is shared with a unidirectional JTAG TMS line.
Ensure that there are no buffers preventing bidirectional communication functionality.
The Serial Wire Clock pin clocks data into and out of the target during debugging.
The Serial Wire Output pin provides trace data to DSTREAM-ST. You are advised to series terminate
SWO close to the target processor.
The Voltage Target Reference pin supplies DSTREAM-ST with the debug rail voltage of the target to
match its I/O logic levels. VTRef can be tied HIGH on the target.
Note
If VTRef is pulled HIGH by a resistor, its value must be no greater than 100Ω.
Ground.
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
2 ARM
2.1 About the ARM JTAG 20 connector pinouts and interface signals
®
Table 2-2 ARM JTAG 20 signals (continued)
Non-Confidential
DSTREAM-ST target interface connections
®
2-21