About Jtag Port Timing Characteristics; Figure 2-6 Jtag Port Timing Diagram - ARM DSTREAM-ST System And Interface Design Reference Manual

2.5

About JTAG port timing characteristics

The JTAG port timing characteristics of the DSTREAM-ST unit are in-line with the requirements of the
IEEE 1149.1 specification.
TMS and TDI are setup by the DSTREAM-ST unit on the falling edge of TCK. This is then sampled by
the target on the rising edge of TCK. Ideally, the target device must output TDO signal on the falling
edge of TCK for DSTREAM-ST to sample it on the next rising edge of TCK.
Any delays in TDO are not critical, but might reduce the maximum frequency of the JTAG interface.
These timings are considered correct at the target JTAG connector. Delays that are introduced by the
JTAG cable are compensated for within the DSTREAM-ST unit.
Since all signals are setup on the falling edge of TCK and sampled on the rising edge, the effective setup
and hold times for the target device and the DSTREAM-ST unit is Tclk/2.
The following figure shows the JTAG port timing:
TCK
TDI
TMS
TDO
ARM 100893_0100_00_en
Note
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
2 ARM
Target device
samples TDI and
TMS
T
clk
Non-Confidential
DSTREAM-ST target interface connections
®
2.5 About JTAG port timing characteristics
Target device sets-up
TDO

Figure 2-6 JTAG port timing diagram

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