Figure 2-4 Swd Timing Diagrams - ARM DSTREAM-ST System And Interface Design Reference Manual

Read cycle
DSTREAM output to
SWDIO
DSTREAM output to
SWDCLK
Target output to SWDIO
Write cycle
DSTREAM output to
SWDIO
DSTREAM output to
SWDCLK
Target output to SWDIO
The DSTREAM-ST unit writes data to SWDIO on the falling edge of SWDCLK. The DSTREAM-ST
unit reads data from SWDIO on the rising edge of SWDCLK. The target writes data to SWDIO on the
rising edge of SWDCLK. The target reads data from SWDIO on the rising edge of SWDCLK.
The following table shows the timing requirements for the SWD:
Parameter Min Max
T 10ns
high
T
10ns
low
T
-5ns
os
T
4ns
is
T
1ns
ih
ARM 100893_0100_00_en
Stop Park
T high T lo w
T os
Tri-State
Stop Park
T is
Tri-State
Description
500μs SWDCLK HIGH period
500μs SWDCLK LOW period
5ns SWDIO Output skew to falling edge SWDCLK
- Input Setup time required between SWDIO and rising edge SWDCLK
- Input Hold time required between SWDIO and rising edge SWDCLK
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
2 ARM
Tri-State
Acknowledge
Tri-State
T ih
Acknowledge Data
Non-Confidential
DSTREAM-ST target interface connections
®
2.3 About Serial Wire Debug (SWD)
Data Data
Tri-State
Data Parity

Figure 2-4 SWD timing diagrams

Table 2-5 SWD timing requirements
Parity Start
Start
Tri-State
2-26