Signal Requirements; Figure 4-2 Data Waveforms; Data Setup And Hold - ARM DSTREAM-ST System And Interface Design Reference Manual

4.3

Signal requirements

Use the information below to understand the data setup and hold requirements, and switching thresholds
for the ARM DSTREAM-ST unit.

Data setup and hold

The following figure and table show the setup and hold timing of the trace signals with respect to
TRACECLK.
Parameter
Tsh (min)
Thh (min)
Tsl (min)
Thl (min)
DSTREAM-ST supports DDR clocking mode. Data is output on each edge of the TRACECLK signal
and TRACECLK (max) <= 300MHz.
Switching thresholds
The DSTREAM-ST senses the target signaling reference voltage (VTRef) and automatically adjusts its
switching thresholds to VTRef/2. For example, on a 3.3V target system, the switching thresholds are set
to 1.65V.
ARM 100893_0100_00_en
DDR
TRACECLK
DSTREAM-ST
0.75ns
0.75ns
0.75ns
0.75ns
Note
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
4 Target board design for tracing with ARM
DATA
Tsh
Description
Data setup high
Data hold high
Data setup low
Data hold low
Non-Confidential
DSTREAM-ST
®
4.3 Signal requirements
Thh Tsl

Figure 4-2 Data waveforms

Table 4-1 Data setup and hold
Thl
4-44