Modeling - ARM DSTREAM-ST System And Interface Design Reference Manual

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4.4

Modeling

For trace bit rates of 0-600Mbps, basic signal integrity can be established using simplified modeling. The
bulk of the transmission line model consists of the cable used between the DSTREAM-ST unit and the
target.
The 30cm CoreSight cable is made using 0.635mm pitch ribbon and can be modeled as a 66Ω
transmission line with a 1.5ns propagation delay and 0.4Ω DC resistance. The connectors at either
end can be modeled as a 0.5pF capacitance to ground.
The 15cm CoreSight cable is made using 0.635mm pitch ribbon and can be modeled as a 66Ω
transmission line with a 0.75ns propagation delay and 0.2Ω DC resistance. The connectors at either
end can be modeled as a 0.5pF capacitance to ground.
The JTAG 20 cable is made using 1.27mm pitch ribbon and can be modeled as a 100Ω transmission
line with a 1.5ns propagation delay and 0.1Ω DC resistance. The connectors at either end can be
modeled as a 1.0pF capacitance to ground.
The circuit at the DSTREAM-ST unit end of the transmission line can be modeled using the following
primitives:
All resistors can be modeled as their ideal resistance values with minimum/zero parasitics.
All capacitors can be modeled as their ideal capacitance values with minimum/zero parasitics.
Input comparators can be modeled using the Spartan 3 SSTLx_I model. The switching threshold can
be assumed to be half of the VTRef voltage as supplied by the target and data can be assumed to be
valid when it is 100mV above or below this threshold.
Output drivers can be modeled using the Spartan 3 LVCMOS Fast 16mA model. The model voltage
must be chosen to match the target system voltage.
All other parasitics and traces within the DSTREAM-ST are negligible for most practical purposes.
You are strongly advised to use series termination on all target outputs to achieve good signal integrity.
ARM 100893_0100_00_en
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4 Target board design for tracing with ARM
DSTREAM-ST
®
4.4 Modeling
4-45

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