Physical And Electrical Connection Guidelines; Figure 1-3 Typical Jtag Connection Scheme - ARM DSTREAM-ST System And Interface Design Reference Manual
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1.3
Physical and electrical connection guidelines
Use the guidelines below to define physical and electrical connections on your target board.
JTAG connection scheme
The diagram shows a typical JTAG connection scheme.
•
The signals TDI, TMS, TCK, RTCK and TDO are typically pulled up on the target board to keep
them stable when the debug equipment is not connected.
•
DBGRQ and DBGACK if present, are typically pulled down on the target.
•
If there is no RTCK signal provided on the processor, it can either be pulled to a fixed logic level or
connected to the TCK signal to provide a direct loop-back.
•
All pull-up and pull-down resistors must be in the range 1K-100KΩ.
•
The VTRef signal is typically connected directly to the VDD rail. If you use a series resistor to
protect against short-circuits, it must have a value no greater than 100Ω.
•
To improve signal integrity, it is good practice to provide an impedance matching resistor on the
TDO and RTCK outputs of the processor. The value of these resistors, added to the impedance of the
driver must be approximately equal to 50Ω.
Target interface logic levels
DSTREAM-ST is designed to interface with a wide range of target system logic levels. It does this by
adapting its output drive and input threshold to a reference voltage supplied by the target system.
VTRef feeds the reference voltage to the DSTREAM-ST unit. This voltage is clipped internally at
approximately 3.4V, and is used as the output high voltage (Voh) for logic 1s (ones) on TCK, TDI, and
TMS.
For logic 0s (zeroes), 0V is used as the output low voltage. The input logic threshold voltage (Vi(th)) for
the TDO, RTCK, and nSRST input is 50% of the Voh level, and so is clipped to approximately 1.7V.
The relationships of Voh and Vi(th) to VTRef are shown in the following figure:
ARM 100893_0100_00_en
VTREF
TDI
TMS
TCK
RTCK
TDO
nTRST
nSRST
DBGRQ
DBGACK
GND
Note
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1 ARM
1.3 Physical and electrical connection guidelines
VDD
Gnd
Gnd
Gnd
Figure 1-3 Typical JTAG connection scheme
Non-Confidential
DSTREAM-ST system design guidelines
®
Processor/
TDI
TMS
TCK
22R
RTCK
22R
TDO
TRST
Reset
circuit
RESET
DBGRQ
DBGACK
ARM
ASIC
1-17
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