Hc05Evs Limitations - Motorola M68EM05P18 User Manual

HC05EVS Limitations

M68EM05P18UM/D
MOTOROLA
Limitations that apply to using your M68EM05P18 in an HC05EVS are
explained here.
1. CLI/RTI. You cannot trace a clear interrupt mask (CLI) or return
from interrupt (RTI) instruction with an interrupt enabled and
pending, due to MCU interrupt handling. Attempting such a trace
causes an interrupt in the monitor map, which forces a software
reset of the HC05EVS. User breakpoints remain in the user map
as SWI instructions; you must remove such SWI instructions.
2. Branch. Do not trace a conditional branch instruction (such as
BRCLR) that branches to itself. Because the monitor places an
SWI instruction on the object of the branch, the system never
would execute the instruction. However, it would appear to you
that the instruction had executed. You can enter a GO command
while the PC points to this type of instruction as long as the
instruction is not a breakpoint address.
3. IRQ/SWI. Whenever possible, avoid mixing interrupt requests
(IRQs) and user software interrupts (SWIs) to prevent a possible
IRQ-SWI timing problem. A concurrent hardware interrupt and
SWI could cause an HC05EVS failure that could stop program
execution. To recover from such a failure (which occurs
infrequently), press the master reset switch (SW3).
4. Memory Map. You must be aware of the memory map of the MCU
being emulated and be sure to use only valid ROM locations. The
HC05EVS does not provide protection to limit user programs to
the exact amount of MCU ROM available. (For information about
memory maps, consult the technical data book for the MCU.)
5. COP. The computer operating properly (COP) update register
serves as a ROM location for the resident MCU. Accordingly, the
platform board write-protect jumper header must enable write
protection. Otherwise, any writes to the COP update register
change the value stored in user pseudo ROM.
HC05EVS Configuration and Operation
HC05EVS Configuration and Operation

HC05EVS Limitations

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