Motorola M68EM05P18 User Manual page 18

General Description
Table 2. Logic Analyzer Connector J1 Signal Descriptions
Pin
1, 3, 4, 12, 14, 31, 33,
34, 35, 36, 40
2, 6
5, 7, 9, 11, 13, 15, 17,
19, 21, 23, 25, 27
10, 8
16, 18, 20, 22, 24, 26,
28, 30
29
32
37
38
39
18
Connector Information
Mnemonic
NC No connection
GND GROUND
LATCHED ADDRESSES (bits 11–0) — MCU latched output address
LA11–LA0
bus
LATCHED ADDRESSES (bits 13–12) — MCU latched output address
LA13, LA12
bus
AD7–AD0 ADDRESS/DATA BUS (bits 7–0) — MCU multiplexed address/data bus
LATCHED READ/WRITE — The MCU's write signal is latched and
LR/W
used on the platform board to control emulator memory accesses.
LOAD INSTRUCTION REGISTER — Active-low signal indicating an
LIR
opcode fetch cycle is in process
V +5 Vdc POWER — Connection to the system voltage V
CC
E CLOCK — Internally generated clock signal used as a timing
E reference. The frequency of E is 1/2 the frequency of input clock
OSC1.
RESET — Active-low signal will be asserted during internally or
RESET
externally caused resets.
General Description
Signal
CC
M68EM05P18UM/D
MOTOROLA