Diskette Controller Registers (Read/Write 3F4 And 3F5) - Adaptec AHA-1740A Technical Reference Manual

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Bit Definition
7 Reserved (set to 0)
6 Reserved (set to 0)
5 Drive B Motor Enable
4 Drive Motor Enable
3 Enable diskette interrupts and DMA
2 Diskette function reset
1 Reserved (set to 0)
0 Drive Select: A "0" on this bit indicates that drive A is selected.

Diskette Controller Registers (Read/write 3F4 and 3F5)

The diskette controller has two main system processor accesses; a status register and
a data register. The 8-bit status register (3F4h), has the status information about the
diskette and may be accessed at any tim. The 8-bit data register (3F5h), which actu-
ally consists of several registers in a stack with only one register presented to the
data bus at a time, stores data, commands, and pareameters, and provides diskette-
drive status information. Data bytes are read from or written to the data register in
order to program or obtain results after a particular command. The main status regis-
ter may only be read and is used to facilitate the transfer of data between the proces-
sor and diskette controller. The bits in the main status register (3F4h) are defined as
follows:
Bit Definition
7 Request for Master (RQM) The data register is ready to send or receive data
to or from the processor.
6 Data Input/Output (DIO) The direction of data transfer between the diskette
controller and the processor. If this bit is a 1, transfer is from the diskette
controller's
data register to the processor; if it is a 0, the opposite is true.
5 Non-DMA mode (NDM) The diskette controller is in the non-DMA mode.
4 Diskette Controller Busy (CB) A read or write command is being executed.
3 Reserved (set to 0)
2 Reserved (set to 0)
1 Diskette Drive B Busy (DBB) Diskette drive B is in the seek mode
0 Diskett Drive A Busy (DAB) Diskette drive A is in the seek mode.
The diskette controller can perform eleven different commands. Each command is in-
itiated by a multibyte transfer from the processor, and the result after execution of
the command may also be a multibyte transfer back to the processor. Because of this
multibyte interchange of information between the diskette controller and the proces-
sor, each command can be considered to consist of three phases:
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AHA-1740A/1742A/1744