I/O Port Register Standard Mode (Group 1) - Adaptec AHA-1740A Technical Reference Manual

EISA-to-Fast SCSI Host Adapter
Reserved Registers
The following registers are reserved for future use.
Reserved 0 (RESV0, zCC5, W/R)
Reserved 1 (RESV1, zCC6, W/R)
Reserved 2 (RESV2, zCC7, W/R)

I/O Port Register Standard Mode (Group 1)

The I/O Control Standard Mode (Group 1) registers form the primary communication
channel between the system and the adapter for Standard Mode operation. When
power is initially applied, these registers will not respond to system accesses.
EBCTRL, bit 0, must be set before access is allowed.
These registers are not writable or readable until the CDEN bit in the control regis-
ter is set. Refer to the section titled Expansion Board Control Register. The eight-bit
port registers form the primary communications channel and are addressed with ref-
erence to a base address, plus offset. There are three I/O ports which reside in ISA
I/O address space. The base address is selected by writing to the PORTADDR
register.
Base+0 Control and status
Base+1 Command and data
Base+2 Interrupt information
The Control/Status Port controls the host adapter. The bits can initiate hardware or
firmware operation directly. The Control Port allows the system to control the host
adapter hardware, such as executing a hardware reset. The Status Port provides
status about the state of the host adapter firmware and hardware.
The host adapter supports commands sent directly to I/O address space through
CMD/DAT. LAVAIL indicates that the write port is full and should be sampled for
zero before writing to CMD/DAT. HAVAIL indicates that the read port is full and
should be sampled for one before reading from CMD/DAT. The low-level commands
are executed by placing the appropriate command byte followed by any additional pa-
rameters into CMD/DAT. Parameters are then transferred from the host adapter
through port I/O or into the system through Bus Master transfers to provide the infor-
mation necessary to complete the command.
In response to a reset, if the host adapter passes diagnostics, then the local processor
will set POCIP (LSTAT bit 7) to zero and INITRQD (LSTAT bit 5) to one. These bits
are available in the system STATUS register and this state means that mailbox in-
itialization may proceed. Additional parameters are passed via the CMDDAT
register.
If the host adapter fails diagnostics, then the local processor will set POCIP (LSTAT
bit 7) to zero and POCFAIL (LSTAT bit 6) to one. These bits are available in the
Hardware Functional Description
4-17