Bus Master Dma; Scsi Interface And Protocol Chip (Aic-6251) - Adaptec AHA-1740A Technical Reference Manual

adaptec

Bus Master DMA

The AHA-1740A/1742A/1744 controls the host EISA bus as a master and transfers
data directly to and from main system memory. This implementation is known as
Bus Master DMA. Bus Master DMA greatly reduces the host software overhead be-
cause the host CPU is no longer required to maintain the DMA channel's address
pointers and word counts. Bus Master DMA also reduces the number of interrupts
generated per I/O command. The Intel BMIC includes the functions of the DMA
controller.
Adaptec's implementation of Bus Master DMA can achieve a 33 MByte/second burst
data rate. This speed is especially valuable in multitasking systems where the tasks
execute on a time shared basis. Appendix A, Memory Cycle Timing Diagram shows a
diagram of the timing required to achieve the DMA rates that are supported by the
AHA-1740A/1742A/1744.
The host adapter uses burst cycles on the EISA bus if the memory supports the trans-
fer by asserting SLBURST*. If not, the host adapter will use 32-bit wide data trans-
fers with the normal 2 cycle timing. The adapter relies on system translation logic
when reading or writing 16-bit expansion board memory in nonburst mode.
The AHA-1740A/1742A/1744 DMA hardware will handle both odd-byte and odd-
memory address data transfers with no performance degradation. The adapter has
the ability to align bytes when the starting address is not a multiple of four or the
byte count is an odd value. It will transfer 1, 2, or 3, bytes at the beginning or end of
the transfer so that 32-bit burst cycles may be used.
The adapter will also be an 8-bit I/O slave with registers for use during setup and op-
eration. Two modes of operation are defined which are mutually exclusive. The two
modes are the AHA-1540 Standard Mode and the AHA-1740 Enhanced Mode. The
current AHA-1540 ISA register set is implemented for software compatibility. The
I/O address is selected by programming a configuration register. AHA-1740 En-
hanced Mode is implemented to give extended addressing ability as well as addi-
tional SCSI-2 features not available in Standard Mode. Several configuration
registers are implemented in EISA I/O space to allow autoconfiguration.
The user may program the adapter to use interrupts 9, 10, 11, 12, 14, and 15. The in-
terrupt may also be programmed to a high or low level. When the high level is used,
the board will be compatible with the ISA implementation, and current drivers.
When the low level is used, the interrupt may also be shared and EISA drivers may
be written to use multiple boards on the same interrupt.

SCSI Interface and Protocol Chip (AIC-6251)

The host adapter supports SCSI functions that are a superset of Adaptec's AT
1540 family) and Micro Channel
ports new SCSI-2 features such as tagged queuing and 10 MBytes/second data
transfers (Fast SCSI). In particular, the adapter supports synchronous negotiation to
10 MBytes, up to an offset of seven, and it will support the Modify Data Pointers ex-
tended message, Tagged Queuing, and Contingent Allegiance. Note that fast,
2-2
®
(AHA-1640) host adapters. The AHA-1740 sup-
AHA-1740A/1742A/1744
®
(AHA-