Principles Of Operation; Task Queuing - Adaptec AHA-1740A Technical Reference Manual

adaptec
Please refer to the SCSI specification ANSI X3.131, the Common Command Set
(CCS) revision 4B, and the SCSI-2 draft for additional information on Command De-
scriptor Blocks.

Principles of Operation

At power-up, the host must inform the host adapter of the location and number of
mailboxes. To start a task, the host builds a CCB and stores its memory address into
a free mailbox. A nonzero Mailbox Out command byte is then written to indicate that
the mailbox entry is full and valid. The host then writes to an I/O port (see Chapter
Four, Hardware Functional Description) to indicate that the host adapter should
scan the MBO area. When a full MBO is found, the host adapter copies the mailbox's
CCB pointer into its internal RAM and clears the mailbox entry by writing a zero to
the MBO command byte. This frees the MBO so that it can be used to start another
task.
After completing a task, the host adapter scans the MBI area for a free mailbox.
When one is found, it is updated with the task's completion status and CCB pointer.
The CCB pointer identifies the completed task. An MBI stored interrupt is generated
to notify the host that a task has been completed. The host scans the MBI area
searching for a nonzero Status byte. When one is located, the host obtains the CCB
pointer and frees the MBI by writing a zero into the Status byte. The host then exam-
ines the contents of the CCB to determine that the command was successfully com-
pleted. The freed MBI can now be used to indicate the completion of another task.
The host adapter fills the MBI area and scans the MBO area in a round-robin fash-
ion. If the host saves the position of the last active MBI entry, it can determine the
MBI of a new entry immediately without searching, since a new entry will be in the
next MBI location.
The host adapter transmits a new MBO Available or MBI Full interrupt to the host
whenever all non-mailbox interrupts have been cleared and serviced by the host. The
host should analyze the interrupts and clear them as soon as possible so that the host
adapter can post any new interrupts quickly. The host adapter will not wait until an
interrupt can be transmitted to the host before processing an MBO entry or creating
a new MBI entry. Thus, in processing a single MBI interrupt, the host may find sev-
eral MBI entries waiting by the time the interrupt processing is finished. Similarly, a
later MBI interrupt for the last of the later MBI entries may find nothing to service
because the MBI entry was examined and processed as a result of the first MBI Full
interrupt. If the interrupts are reset quickly by the host, the probability of an inter-
rupt occurring when no MBI entry is available is much lower, providing an important
performance improvement. If the MBI entries are emptied by the host in a round-
robin order, the scan for the next full entry is very simple, since it is always the next
MBI entry in the mailbox area.

Task Queuing

Multiple tasks may be started against a target/LUN or against multiple targets/Logi-
cal Units. Since only one task can be active against any one LUN at a time, all other
tasks for the same LUN are queued. Other LUNs may have active tasks at the same
time.
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AHA-1740A/1742A/1744