Diskette Registers; Digital Output Registers (Write 3F2) - Adaptec AHA-1740A Technical Reference Manual

EISA-to-Fast SCSI Host Adapter
Enhanced Mode (Group 2) Status (G2STAT, zCD7, R)
Bit Definition
7-3 Reserved
2 Mailbox out empty Set to one by firmware when it is done with the mailbox out.
Cleared by software writing to any mailbox out location.
1 Interrupt pending Reflects the state of the EISA interrupt line from the Enhanced
Mode (Group 2) interrupt before the enable/disable logic.
0 Busy Set by a write to the Attention register or a hard reset. Cleared when the
firmware reads the Attention register.
Enhanced Mode (Group 2) Status 2 (G2STAT2, zCDC, R)
Bit Definition
7-1 Unused
0 Host Ready This bit is set by the host (G2CNTRL bit 5) to indicate that it has
loaded the next data group into the mailbox out or that it has read the data group
from the mailbox in. This bit is used during Immediate command execution and
need not be set during normal operation. It is cleared by the adapter when all
pending information is processed.

Diskette Registers

The host communicates with the floppy disk controller via the set of registers defined
below:
I/O Address
Primary (hex)
3F2
3F4
3F5
3F7

Digital Output Registers (Write 3F2)

The digital output register (DOR) is a write-only register used to control drive mo-
tors, drive selection, and feature enable. All bits are cleared by the I/O interface reset
line.
The bit definitions follow:
Secondary (hex) Read
372 —
374 Main status
375 Diskette data
377 Digital input
Note
Channel reset clears all bits.
Hardware Functional Description
Write
Digital Out
Main status
Diskette data
Diskette Ctrl
4-23