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base +
15
14
20 16
Write
ch15 ch14 ch13 ch12 ch11 ch10
Read
base +
15
14
22 16
Write
ch31 ch30 ch29 ch28 ch27 ch26 ch25 ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 ch16
Read
base +
15
14
24 16
Write
ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32
Read
base +
15
14
26 16
Write
ch63 ch62 ch61 ch60 ch59 ch58 ch57 ch56 ch55 ch54 ch53 ch52 ch51 ch50 ch49 ch48
Read
base +
15
14
28 16
Write
Read
:ULWH D ³´ WR FORVH D FKDQQHO ZULWH D ³´ WR RSHQ D FKDQQHO
5HDGLQJ WKH FKDQQHO ELW LQGLFDWHV WKH VWDWH RI WKH UHOD\ GULYHU FLUFXLW RQO\ ,W FDQQRW GHWHFW D
GHIHFWLYH UHOD\
bit 0
VSA (ch90)
bit 1
VSB (ch91)
bit 2
CS (ch92)
bit 3
RTA (ch93)
bit 4
RTB (ch94)
106 Register-Based Programming
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For example, to connect both bank A and bank B to the analog bus, write a
"1" to bits 0 and 1 of the Tree Relay Control Register (base + 28
channel 90 (VSA) and channel 91 (VSB). All other bits must be set to "0".
13
12
11
10
9
ch9
13
12
11
10
9
13
12
11
10
9
13
12
11
10
9
13
12
11
10
9
undefined
undefined
Tree Relay Control Bits
Connects the Voltage Sense H-L-G terminals of the Analog Bus to Bank A.
Connects the Voltage Sense H-L-G terminals of the Analog Bus to Bank B.
Connects the Current Source H-L-G terminals of the Analog Bus to Bank B.
Connects the Reference Thermistor to Bank A for voltage sense.
Connects the Reference Thermistor to Bank B for current source.
8
7
6
5
ch8
ch7
ch6
ch5
ch4
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
RTB
ch94
) to close
16
4
3
2
1
0
ch3
ch2
ch1
ch0
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
RTA
CS
VSB
VSA
ch93
ch92
ch91
ch90
Appendix B
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