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3.2.3.15 Manufacturing signals
®
According to Qseven
Standard specifications, rel. 2.0, on pin designed as MFG_NCx (pins 204, 207÷210) are carried the JTAG signal necessary to program Q7-
928 internal FPGA.
Pins 208 and 209 are multiplexed, according to the above mentioned specifications, with NXP i.MX6 Internal UART #3 signals TX and RX.
Selection between JTAG and UART DEBUG signals is made by driving the MFG_NC4 signal carried on pin 204, with the following meaning:
MFG_NC4 signal level
Pin 208 (MFG_NC2) signal
LOW
UART_DEBUG_RX
HIGH
JTAG_TDI
In case MFG_NC4 signal is not driven externally, then an internal pull-down makes available UART_DEBUG_RX and UART_DEBUG_TX signals on pin 208 and
209.
MFG_NC0 is always connected to JTAG_TCK, while MFG_NC3 is always connected to JTAG_TMS.
Please remember that JTAG interface is connected to Q7-928 embedded CPLD, not to the i.MX6 processor's JTAG interface. JTAG
interface available on MFG_NCx pins is reserved only for manufacturing phase; it must not be used by the customer.
In case it is necessary to trace the software using any JTAG debugger, it is possible to provide Q7-928 module configured with i.MX6 JTAG
port accessible on MFG_NCx pins. Please contact your Sales Representative for this.
Q7-928
Q7-928 User Manual - Rev. First Edition: 1.0 - Last Edition: 3.0 - Author: S.B. - Reviewed by P.Z Copyright © 2016 SECO S.r.l.
Pin 209 (MFG_NC1) signal
UART_DEBUG_TX
JTAG_TDO
40
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