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SPI
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3.2.3.1 PCI Express interface signals
Q7-928 can offer one PCI Express lane, which is directly managed by i.MX6 processor (all versions).
PCI express Gen 2.0 (5Gbps) is supported. Of the previous generation, only PCI express 1.1 is supported.
Here following the signals involved in PCI express management
PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair
PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair
PCIE_CLK_REF+ / PCIE_CLK_REF-: PCI Express Reference Clock for lane #0, Differential Pair
®
PCIE_WAKE#: Qseven
Module's Wake Input, it must be externally driven by devices requiring waking up the system. Since it is an Active-Low Input to the
module, this signal is pulled-up with a 10kΩ resistor to +3.3V_A power rail. On the carrier board, connect it directly to the PCI-e/miniPCI-e connector's WAKE#
signal, or to WAKE# signal of any eventual PCI-e Controller present on the Carrier Board.
PCIE_RST#: Reset Signal that is sent from Qseven
47kΩ resistor; it can be used directly to drive externally a single RESET Signal. In case it is necessary to supply Reset signal to multiple devices, provide for a
buffer on the carrier board.
Q7-928
Q7-928 User Manual - Rev. First Edition: 1.0 - Last Edition: 3.0 - Author: S.B. - Reviewed by P.Z Copyright © 2016 SECO S.r.l.
SPI_MISO
SPI_CLK
+5V_A
MFG_NC0
MFG_NC1
+5V_S
+5V_S
+5V_S
+5V_S
+5V_S
+5V_S
+5V_S
+5V_S
+5V_S
+5V_S
®
Module to any PCI-e device available on the carrier board. It is a 3.3V active-low signal, tied to GND via a
201
202
SPI_CS1#
203
204
MFG_NC4
205
206
+5V_A
207
208
MFG_NC2
209
210
MFG_NC3
211
212
+5V_S
213
214
+5V_S
215
216
+5V_S
217
218
+5V_S
219
220
+5V_S
221
222
+5V_S
223
224
+5V_S
225
226
+5V_S
227
228
+5V_S
229
230
+5V_S
O
SPI
N.A.
MFG
PWR
N.A.
MFG
N.A.
MFG
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