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GP_PWM_OUT1: General Purpose PWM output, +3.3V_S voltage signal, directly managed by Lattice LCMXO640 CPLD.
GP_PWM_OUT2 General Purpose PWM output, +3.3V_S voltage signal. It is connected to i.MX6 processor PWM2 functional output.
SMB_CLK: SM Bus control clock line for System Management. Bidirectional signal, electrical level +3.3V_S with a 4k7Ω pull-up resistor. It is managed by i.MX6
processor's I2C1 controller.
SMB_DAT: SM Bus control data line for System Management. Bidirectional signal, electrical level +3.3V_S with a 4k7Ω pull-up resistor. It is managed by i.MX6
processor's I2C1 controller.
GP0_I2C_CLK: general purpose I2C Bus clock line. Bidirectional signal, electrical level +3.3V_S with a 4k7Ω pull-up resistor. It is managed by i.MX6 processor's
I2C3 controller.
GP0_I2C_DAT: general purpose I2C Bus data line. Bidirectional signal, electrical level +3.3V_S with a 4k7Ω pull-up resistor. It is managed by i.MX6 processor's
I2C3 controller.
Regarding the i.MX6 I2C buses, please refer to the following table.
Bus
Bus Number / device
SM Bus
I2C_1/I2C-0
HDMI_DDC
I2C_2/I2C-1
I2C
I2C_3/I2C-2
Q7-928
Q7-928 User Manual - Rev. First Edition: 1.0 - Last Edition: 3.0 - Author: S.B. - Reviewed by P.Z Copyright © 2016 SECO S.r.l.
MXM Pins
Address Locked (@7 bit)
60: SMB_CLK
0x40
62: SMB_DAT
150: HDMI_CTRL_DAT
0x50 (if HDMI Driver is enabled)
152: HDMI_CTRL_CLK
66: GP0_I2C_CLK
0x3C (if MIPI_CSI driver for OV5640 camera is enabled)
68: GP0_I2C_DAT
39
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