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3.2 Connectors description
3.2.1
FFC/FPC Camera Interface
CAMERA CONNECTOR - CN2
Pin
Signal
Pin
1
CAM_XCLK_A
19
2
GND
20
3
---
21
4
GND
22
5
CAM_PCLK
23
6
CAM_VS
24
7
CAM_HS
25
8
CAM_FLD
26
9
GND
27
10
CSI0_DAT12
28
11
CSI0_DAT13
29
12
CSI0_DAT14
30
13
CSI0_DAT15
31
14
CSI0_DAT16
32
15
CSI0_DAT17
33
16
CSI0_DAT18
34
17
CSI0_DAT19
35
18
CSI0_DAT10
36
Q7-928
Q7-928 User Manual - Rev. First Edition: 1.0 - Last Edition: 3.0 - Author: S.B. - Reviewed by P.Z Copyright © 2016 SECO S.r.l.
NXP i.MX6 Processor includes an Image Processing Subsystem, that can be used for video
applications, like video-preview, video recording and frame grabbing.
The access to the video input port comes through an FFC/FPC connector, type HIROSE p/n
Signal
FH12A-36-S-0.5SH(55), which is able to accept 36 poles 0.5mm pitch FFC cables.
CSI0_DAT11
On the same connector are carried:
CSI0_D2_DN
-
CSI0_D2_DP
CSI2IPU gasket.
CAM_GPIO_A
-
GP0_I2C_CLK
Both video inputs can work independently and simultaneously.
GP0_I2C_DAT
For i.MX6 Solo and Dual Lite processors, CSI port is limited to 2 lanes only.
CAM_RESETB
Here following is shown the meaning of various pins of the connector.
GND
Pins[1÷17]: 8-bit parallel format arranged to guarantee 8-bit alignment LSB for ITU BT-656
CSI0_D3_DN
format; voltage level: +3.3V_CAM.
CSI0_D3_DP
Pins[18÷19]: additional pins for 10-bit format; voltage level: +3.3V_CAM.
+3.3V_CAM
Pins[22÷25]: GPIO/CAM I2C; voltage level: +3.3V_CAM
+3.3V_CAM
Pins[29÷30]: +3.3V_CAM
CSI0_CLK0_DN
Pins [31÷36]: MIPI CSI first channel (Clock+2 lanes)
CSI0_CLK0_DP
Pins [20÷21; 27÷28]: MIPI CSI additional lanes (only for i.MX6 Dual and i.MX6 Quad)
CSI0_D0_DN
CSI0_D0_DP
CSI0_D1_DN
CSI0_D1_DP
a 10-bit parallel port, supporting ITU-R BT.656 and so on, managed by i.MX6
MIPI CSI (Camera Serial Interface) Port.
22
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