Seco Q7-928 User Manual page 33

Qseven rel. 2.0 compliant module with nxp i.mx6 processor

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HDA_BCLK: AC'97 Serial Bit Clock signal. Output from the module to the Carrier board, electrical level +3.3V_S.

HDA_SDO: AC'97 Serial Data Out signal. Output from the module to the Carrier board, electrical level +3.3V_S.

HDA_SDI: AC'97 Serial Data In signal. Input to the module from the Carrier board, electrical level +3.3V_S.

All these signals have to be connected, on the Carrier Board, to an AC'97 Audio Codec. Please refer to the chosen Codec's Reference Design Guide for correct

implementation of audio section on the carrier board.

3.2.3.8 LVDS Flat Panel signals

Embedded into NXP i.MX6 processor there is an LVDS Display Bridge, connected to the Image Processing Unit (IPU), that makes externally available two LVDS

channels, each one consisting of 1 clock pair and four data pairs.

It is possible to configure LVDS output so that it can be used as:

One single channel (18 or 24 bit) output, max resolution supported 1366 x 768 @ 60fps

One dual channel (18 or 24 bit) output, max resolution supported 1920 x 1200 @ 60fps

Two identical single channel outputs, max resolution supported 1366 x 768 @ 60fps

Two independent single channel outputs, max resolution supported 1366 x 768 @ 60fps on each channel

All of these possibilities come by opportunely configuring the O.S. installed on the module.

Here following the signals related to LVDS management:

LVDS_A0+/LVDS_A0-: LVDS Channel #0 differential data pair #0.

LVDS_A1+/LVDS_A1-: LVDS Channel #0 differential data pair #1.

LVDS_A2+/LVDS_A2-: LVDS Channel #0 differential data pair #2.

LVDS_A3+/LVDS_A3-: LVDS Channel #0 differential data pair #3.