Seco Q7-928 User Manual page 36

Qseven rel. 2.0 compliant module with nxp i.mx6 processor

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3.2.3.10 LPC/GPIO interface signals

According to Qseven

specifications rel. 2.0, on the golden edge finger connector there are 8 pins that can be used for implementation of Low Pin Count (LPC)

Bus interface or as General Purpose I/Os (GPIO).

Please consider that LPC interface is not native for i.MX6 processors, it is derived from embedded LCMXO640 CPLD instead.

Depending on the firmware programmed on that CPLD, it is possible to have available LPC or GPIO interface.

Please take care of specifying if LPC interface or GPIOs are needed, before placing an order of Q7-928 module.

When the Board is programmed for LPC Interface, following signals will be available:

LPC_AD[0÷3]: LPC data bus, bidirectional signal, +3.3V_S electrical level.

LPC_CLK: LPC Clock Output line, +3.3V_S electrical level. Since only a clock line is available, if it is necessary to connect more LPC devices on the carrier board,

then provide for a zero-delay clock buffer to connect all clock lines to the single clock output of Qseven

LPC_FRAME#: LPC Frame indicator, active low output line, +3.3V_S electrical level. This signal is used to signal the start of a new cycle of transmission, or the

termination of existing cycles due to abort or time-out condition.

LPC_LDRQ#: LPC DMA request, active low input line, +3.3V_S electrical level. This signal is used only by peripherals requiring DMA or bus mastering

SERIRQ: LPC Serialised IRQ request, bidirectional line, +3.3V_S electrical level. This signal is used only by peripherals requiring Interrupt support.

When the board is programmed for GPIOs, all previous signals are not available and corresponding pins on Qseven

I/Os, bidirectional signals at +3.3V_S electrical level. Programming of these GPIOs can be made using dedicated APIs supplied by SECO, or through Linux File

System.

3.2.3.11 SPI interface signals

i.MX6 processors offer up to four Enhanced Configurable Serial Peripheral Interfaces (eCSPIS), which can be used for connection of EEPROMs and Serial Flash

devices, which can also be used for serial boot.

SPI interface can support speed up to 20MHz.

Signals involved with SPI management are the following:

SPI_MOSI: SPI Master Out Slave In, Output from Qseven

SPI_MISO: SPI Master In Slave Out, Input to Qseven

SPI_CLK: SPI Clock Output to carrier board's SPI embedded devices. Electrical level +3.3V_S

SPI_CS0#: SPI primary Chip select, active low output signal (+3.3V_S electrical level)

SPI_CS1#: SPI secondary Chip select, active low output signal (+3.3V_S electrical level). This signal must be used only in case there are two SPI devices on the

carrier board, and the first chip select signal (SPI_CS0#) has already been used. It must not be used in case there is only one SPI device.

Q7-928

module to SPI devices embedded on the Carrier Board. Electrical level +3.3V_S

module from SPI devices embedded on the Carrier Board. Electrical level +3.3V_S

module.

golden finger connector are General Purpose