Port Setting - NEC 78K0S/K 1+ Series Application Note

4.6

Port Setting

Caution The on-chip ports vary, depending on each product, so the ports to be set also vary.
Port 0
Port 2
Port 3
Port 4
Port 12
Port 13
Note P34 is shared with RESET. Selecting the function to be used is set using the option byte. For
details, refer to
(1) Port I/O setting
The PMxx registers are used to set whether ports are to be used as input ports or output ports. Ports are set
as input ports after reset release.
The PMxx format is described, taking the PM2 register as an example.
In this sample program, port 2 is set as described in
2].
PM2
1 1 1
Caution Bits 7 to 4 must be set to 1.
(2) Setting the output port output latch
The Pxx registers are used to set output port output latches to high level or low level. Output port output
latches are set to low-level output after reset release.
The Pxx format is described, taking the P2 register as an example.
In this sample program, port 2 is set as described in
P2
0 0 0
Caution Bits 7 to 4 must be set to 0.
CHAPTER 4 SETTING METHODS
78K0S/KA1+ 78K0S/KB1+
−
P00 to P03
P20 to P23 P20 to P23
Note
P30, P31, P34 P30 to P33, P34
P40 to P45 P40 to P47
P121 to P123 P120 to P123
P130 P130
4.1 Option Byte Setting.
Figure 4-6. Format of Port Mode Register 2 (PM2)
1 PM23 PM22 PM21
Figure 4-7. Format of Port Register 2 (P2)
0 P23 P22 P21
Application Note U18752EJ2V0AN
78K0S/KU1+
−
P20 to P23
Note Note
P32, P34
P40, P43
−
−
[Example 1], mentioned later, and port 4 as in
PM20
Selection of the P2n (n = 0 to 3) pin I/O mode
0 Output mode
1 Input mode
[Example 1], mentioned later.
P20
Selection of the P2n (n = 0 to 3) pin output latch level
0 Low-level output
1 High-level output
78K0S/KY1+
−
P20 to P23
Note
P32, P34
P40 to P47
−
−
[Example
23