NEC 78K0S/K 1+ Series Application Note page 18

[Example 1] f = f = f
CPU XP X
(This is the same as in the sample program setting. In this sample program, "high-speed internal
oscillation clock (8 MHz (TYP.))" is selected as the system clock (f
CPU clock frequency (f
PPCC
0 0 0
PCC
0 0 0
Remark f : System clock frequency
X
The system clock to be used is set using the option byte. For details, refer to
The PPCC register setting value is
"00000000 (bits 0 and 2 to 7 must be set to 0)".
For standard products and (A)-grade products, the detection voltage (V
2.1 V ±0.1 V. To satisfy the condition of "power supply voltage ≥ 2.0 V" (setting condition of the CPU clock
frequency in this sample program) at the point POC is released, the CPU operates normally when this sample
program operates. This is same with (A2)-grade products.
• Assembly language
MOV PPCC, #00000010B
MOV PCC, #00000000B
• C language
PPCC = 0b00000010;
PCC = 0b00000000;
18
CHAPTER 4 SETTING METHODS
/4
) and peripheral hardware clock frequency (f
CPU
0 0 0
0 0 0
"00000010 (bits 2 to 7 must be set to 0)" and the PCC register setting value is
Application Note U18752EJ2V0AN
) by the option byte setting, so the
X
1 0
0 0
PPCC1 PPCC0
1 0
) of the power-on-clear (POC) circuit is
POC
) are 2 MHz (= 8 MHz/4).)
XP
PCC1 CPU Clock Peripheral
Frequency Hardware Clock
(f ) Frequency (f
CPU
0 f /4 f /4
X X
4.1 Option Byte Setting.
)
XP