NEC 78K0S/K 1+ Series Application Note page 10

[Example 2] A crystal or ceramic oscillation clock is used, used as the RESET pin, the low-speed internal oscillator
can be stopped, and the oscillation stabilization time is minimized (2
(This is the same as in Example 1, except for the underlined parts.)
Address: 0080H
1 0 0 1
The option byte setting value is
together with the protect byte setting, the following results.
OPBT CSEG
DB
DB
[Column] What are CSEG (Code Segment), DSEG (Data Segment), and BSEG (Bit Segment)?
CSEG, DSEG, and BSEG are pseudo instructions which indicate where generated codes of instructions,
data, or the like are to be allocated. Instructions and data which are described after such pseudo
instructions have been issued are allocated in the ROM area with a CSEG pseudo instruction, in the RAM
area with a DSEG pseudo instruction, and in the saddr area in RAM with a BSEG pseudo instruction.
For example, to allocate the option byte setting content to addresses starting from 0080H in the internal
ROM (flash memory), first, the CSEG pseudo instruction and AT attribute are used to specify 0080H as the
address. Next, the DB pseudo instruction is used to define values that are to be set to addresses following
0080H, which are then described in the program coded in assembly language.
The DB and DW pseudo instructions can be used only in a ROM area specified with the CSEG pseudo
instruction. Descriptions of the DB or DW pseudo instructions in a RAM area specified with the DSEG or
BSEG pseudo instruction will not cause errors, but must not be used. In this case, an object is generated
and debug operation can be performed, since with MINICUBE2 (on-chip debug emulator) or SM+ (system
simulator), coded instructions and data are expanded to the RAM area. With an actual device, however,
operation is disabled since these cannot be expanded to the RAM area.
For details of the CSEG, DSEG, and BSEG pseudo instructions, refer to the
Manual.
10
CHAPTER 4 SETTING METHODS
1 0 0
"10011000 (bits 4 and 7 must be set to 1)". When the software is described
AT 0080H
10011000B
11111111B
Application Note U18752EJ2V0AN
10
/fx).
0
Control of low-speed internal oscillator oscillation
Oscillation is stopped by software setting
0
(LSRSTOP bit is set to 1).
Selection of system clock source
0 0 Crystal or ceramic oscillation clock (10 MHz (MAX.))
Selection of P34/RESET pin function
1 Used as a RESET pin.
Specification of oscillation stabilization time on power
application or after reset release
10
0 0 2 /fx
RA78K0S Language User's