Xilinx System Generator V2.1 Reference Manual page 126

Xilinx System Generator v2.1 Reference Guide
where
The following table gives examples of Block RAM sizes necessary for various state
machines:
Number of States
Xilinx LogiCORE
This block uses Version 3.2 of the Xilinx Single Port Block Memory LogiCORE.
The block RAM width and depth limitations are described in the core datasheet for
the Single Port Block Memory, which may be found locally at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\blkmemsp_v3_2\do
c\sp_block_mem.pdf
126
N = total number of next state logic block RAM bits
s
k =
log s
2
d = depth of state logic block RAM
s
w = width of state logic block RAM
s
s = number of states
i = number of input bits
Number of
2
4
8
16
32
52
100
Block RAM Bits
Input Bits Needed
5
1
6
5
4
1
4 14336
64
8
1536
2048
2560
768
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