Register - Xilinx System Generator V2.1 Reference Manual

Xilinx System Generator v2.1 Reference Guide
Block Parameters Dialog Box
Figure 3-15: Parallel to Serial block parameters dialog box
Parameters specific to the block are:
An error is reported when the number of output bits does not evenly divide the
number of input bits.
The minimum latency of this block is 1.
Other parameters used by this block are explained in the Common Parameters section
of the previous chapter.
The Parallel to Serial block does not use a Xilinx LogiCORE.

Register

40
Output Order: Most significant word first or least significant word first. Word
size is determined by the size of the input port.
Output Arithmetic Type: unsigned or signed
Number of Input Bits: Input width. Must match size of input port.
Number of Output Bits: Output width. Must divide Number of Input
Bits evenly.
Binary Point: Output binary point location.
The Xilinx Register block models a D flip flop-based register, having
latency of one sample period.
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