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Other parameters used by this block are described in the Common Parameters section
of the previous chapter.
Xilinx LogiCORE
The block always uses the Xilinx LogiCORE: Synchronous FIFO V3.0. The core
datasheet can be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\sync_fifo_v3_0\d
oc\sync_fifo.pdf
ROM
has one input port for the memory address and one output port for data out. The
address port must be an unsigned fixed point integer. The block has two possible
Xilinx LogiCORE implementations, using either distributed or block memory.
Memory
Store Only Valid Data: when checked, the block will not store any invalid
data words; i.e., when the din sample is invalid, the WE (write enable) input is
disregarded (if 1) and the sample is not written into the FIFO.
Zero Initial Output: when checked, initial output from the block is 0.
Otherwise, it is NaN (not a number).
Memory Type: specifies the implementation that must be used either for
distributed or block RAM.
The Xilinx ROM block is a single port read-only memory (ROM).
Values are stored by word and all words have the same arithmetic type,
width, and binary point position. Each word is associated with exactly
one address. An address can be any unsigned fixed point integer from 0
to d-1, where d denotes the ROM depth (number of words). The
memory contents are specified through a block parameter. The block
Xilinx Blocks
107
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