Xilinx System Generator V2.1 Reference Manual page 109

Other parameters used by this block are explained in the Common Parameters section
of the previous chapter.
Xilinx LogiCORE
The block always uses a Xilinx LogiCORE: Single Port Block Memory V3.2 or
Distributed Memory V5.0. For the block memory, the address width must be equal to
where d denotes the memory depth.
The tables below indicate the widths that are acceptable for each depth.
Table: Maximum Word Width for Various Depth Ranges (Virtex/Virtex-E)
Table: Maximum Word Width for Various Depth Ranges (Virtex-II)
When the distributed memory parameter is selected, LogiCORE Distributed Memory
V5.0 is used. The depth must be between 16 and 65536, inclusive for Virtex-II and
Memory
Depth Width
2 to 512
513 to 1024
1025 to 2048
2049 to 4096
4097 to 8192
8193 to 16K
16K+1 to 32K
32K+1 to 64K
64K+1 to 128K
128K+1 to 256K
Depth
2 to 512
513 to 1024
1025 to 2048
2049 to 4096
4097 to 8192
8193 to 16K
16K+1 to 32K
32K+1 to 64K
64K+1 to 128K
128K+1 to 256K
256K+1 to 512K
512K+1 to 1024K
log d
2
256
256
256
192
96
48
24
12
6
3
Width
256
256
256
256
256
192
96
48
24
12
6
3
Xilinx Blocks
109