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Other parameters used by this block are explained in the Common Parameters section
of the previous chapter.
Xilinx LogiCORE
The block always uses the Xilinx LogiCORE Multiply Generator V4.0.
The Core datasheet can be found on your local disk at:
%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\mult_gen_v4_0\do
c\mult_gen.pdf
Inverter
Math
saturated as needed. A positive value is implemented as an unsigned number, a
negative value as signed.
Number of Bits in Constant: specifies the bit location of the binary point of
the constant, where bit zero is the least significant bit.
Multiplier Type: specifies the implementation to be parallel or sequential.
Memory Type: specifies whether to use distributed RAM or block RAM.
Require Maximum Pipelining: when checked, directs System Generator to
pipeline the LogiCORE implementation to the fullest extent possible.
Hardware Over-Sampling Rate: specifies the number of hardware cycles per
input sample; does not affect behavior in simulation, only the hardware
implementation.
Use Placement Information for Core: allows specification of placement
layout shape that will be used when implementing the core in hardware
Placement Style: specifies the layout shape in which the multiplier core will
be placed in hardware. The Rectangular option will generate a rectangular placed
core with loosely placed LUTs. Triangular packing will create a more compact
shape, with denser placement of LUTs.
The Xilinx Inverter block calculates the bitwise logical complement
of a fixed point number. The block can be implemented either as a
Xilinx LogiCORE or as a synthesizable VHDL module.
Xilinx Blocks
85
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