Sync - Xilinx System Generator V2.1 Reference Manual

Figure 3-22: Slice block parameters dialog box showing different options
Parameters specific to the block are:
The Slice block does not use a Xilinx LogiCORE.

Sync

Thus, no data appears on any channel until a first valid sample has been received into
each channel.
Basic Elements
Specify Range As: (Two Bit Locations | Upper Bit Location + Width |Lower
Bit Location + Width). Allows the user to specify either the bit locations of both
end-points of the slice or one end-point along with number of bits to be taken in
the slice.
Width of Slice (Number of Bits): specifies the number of bits to extract.
Top bit of slice Offset by: specifies the offset for the ending bit position
from the LSB, MSB or binary point.
Bottom bit of slice Offset by: specifies the offset for the ending bit
position from the LSB, MSB or binary point.
Relative To: specifies the bit slice position relative to the Most Significant Bit
(MSB), Least Significant Bit (LSB), or Binary point of the top or the bottom of the
slice. Other parameters used by this block are explained in the Common
Parameters section of the previous chapter.
The Xilinx Sync Block synchronizes two to four channels of data so that
their first valid data samples appear aligned in time with the outputs.
The input of each channel is passed through a delay line and then
presented at the output port for that channel. The lengths of the delay
lines embedded in this block, however, are adaptively chosen at the
start of simulation so that the first valid input samples are aligned.
Xilinx Blocks
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