Example Model; Black Box Window - Xilinx System Generator V2.1 Reference Manual

Note - For this example to run correctly, you must change your directory (cd within
the MATLAB console window) to this directory before launching the example model.
The files contained in this directory are:
The example project displays three windows:
By running the simulation from the top-level model, you can see the bits reverse in the
output scope. This simulation is running the MATLAB function bit_reverse.
Figure 4-1: Output of example black box function

Black Box window

The Xilinx Black Box token identifies the top level of your black box.
Double-clicking on this token brings up a window which allows you to
configure the black box.
Open the file bit_reverse.vhd in an editor and view the code. You will
see that the name of the component (bit_reverse) is the same name assigned in the
Black Box block parameters dialog box. The user-defined generic (n_bits) is defined
there as well. The others are default generics that correspond to the ports (DIN and
BRN) on the black box. You must make sure the VHDL code you write (to correspond
with your black box) has component and generic names matching those entered in the
configuration window.
Note - The main:process(DIN)section near the bottom of the VHDL file is
where the actual bit reversing functionality takes place.
Using Black Boxes
black_box.mdl - the Simulink model with an example black box
bit_reverse.m - a MATLAB function for reversing bit order
bit_reverse.vhd - VHDL code for reversing bit order. This file is the actual
black box that must be passed to the Xilinx implementation tools. It imitates the
behavior of the MATLAB function.
The top-level model (a model with black box instantiated in it),
The black box (a new Simulink model), and
The output simulation scopes.
System Generator Software Features
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