Xilinx System Generator V2.1 Reference Manual page 11

The System Generator design flow is shown in the following figure.
Figure 1-1: System Generator design flow diagram
The Xilinx Blockset is accessible in the Simulink library browser, and elements can be
freely combined with other Simulink elements. Only those subsystems denoted as
Xilinx black boxes, and blocks and subsystems consisting of blocks from the Xilinx
Blockset are translated by System Generator into a hardware realization. The
generation process is controlled from the System Generator block found in the Xilinx
Blockset Basic Elements library. The System Generator parameterization GUI allows
the user to choose the target FPGA device, target system clock period, and other
implementation options.
System Generator translates the Simulink model into a hardware realization by
mapping Xilinx Blockset elements into IP library modules, inferring control signals
and circuitry from system parameters (e.g. sample periods), and converting the
The System Generator Design Flow
Library
(including
Xilinx
Blockset)
Simulation
including
S-functions
Synthesis
ENTITY mult IS
GENERIC(w:
PORT(a,b:IN
PORT(y:OUT
END ENTITY
...
VHDL
Synthesis
Compiler
EDIF
FPGA
Place & Route
Bit stream
System Model
Input
1 –
Z
+
k
System Generator
Code Generation Software
- map to IP libraries
- control signals
- VHDL design
- HDL testbench
- constraints
- simulation scripts, project files
Core
Parameters
CORE
Generator
EDIF + Timing
Introduction
MATLAB Environment
Simulink
Output
Simulation
Data
Xilinx
DesignTools
Environment
Test
Vectors
Logic
Simulator
Pass/Fail
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