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Chapter 4:Connecting the Emulator to a Target System
Selecting a clock module
If there is no functional reason why the bus cycle would not complete, check the
timing relationships between the various bus cycle control signals. Probably the
first measurement you will want to make is to see if the assertion of DSACK is
within the emulator specification.
If there are no cycles in the trace list, then the processor stopped during the first bus
cycle. In this case, it is pretty easy to set up the trace using AS as the trigger
because the cycle of interest is the first cycle. If there are only a few cycles in the
trace list, the same technique can be used if the oscilloscope or timing analyzer has
enough depth.
If there are many cycles in the trace list before the processor stalled, use a different
method of triggering. There are a number of different approaches that can be used.
The most direct method is to trigger on a condition of AS low for a period of time
greater than the length of a memory cycle. Another method is to determine if the
system always stops at the same address. This address can then be used as the
trigger. One drawback to this method is that you may have to probe a large number
of signals to get a unique address.
A better way would be to use the emulation-bus analyzer to generate a trigger.
Unfortunately, because the cycle never finishes, the emulation-bus analyzer will
not capture this address, so something preceding this event must be used as the
trigger. Examine the trace list to find a unique event to use as the trigger. Once
you have specified the trigger, you need to configure the emulator to drive the
trigger out. The real trick to cross-triggering is to correlate the trigger event to the
captured data. In this type of measurement, the correlation is easy because the
signals of interest stop transitioning shortly after the trigger occurs.
tg addr=00badad00
tp c
tgout trig2
bnct -r trig2
t
Once you have a trace of the offending cycle, verify that DSACK is present for the
duration required to terminate a cycle. If DSACK is not asserted at all, it could be
an indication that the target system missed the AS. Set up your oscilloscope or
logic analyzer to make a measurement on your cycle start circuitry to determine
why the target system did not respond to the cycle.
If the prompt is "g>" and there are no cycles in the trace list, the target system
never gave the bus to the processor. Check the bus arbitration signals for proper
functionality and timing. Refer to the bus arbitration diagram below. Remember
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