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Cypress PSoC DESIGNER ImageCraft M8C Manual

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ImageCraft Assembly Language Guide
Document # 001-44475 Rev. *B
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl): 408.943.2600
http://www.cypress.com
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  • Page 1 ImageCraft Assembly Language Guide Document # 001-44475 Rev. *B Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com [+] Feedback...
  • Page 2 Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embod- ied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not war- ranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.

  • Page 3: Table Of Contents

    Contents 1. Introduction Chapter Overviews ......................7 Support ........................8 1.2.1 Technical Support Systems................8 1.2.2 Product Upgrades ....................8 Documentation Conventions..................8 Revision History......................9 2. M8C Microprocessor Internal Registers.......................11 Address Spaces......................12 Instruction Set Summary ...................14 Instruction Formats ....................16 2.4.1 One-Byte Instruction ..................16 2.4.2 Two-Byte Instructions..................16 2.4.3 Three-Byte Instructions ..................17 Addressing Modes .....................18 2.5.1 Source Immediate ..................18...
  • Page 4 Contents 4. M8C Instruction Set Add with Carry........................ADC 38 Add without Carry......................ADD 39 Bitwise AND ........................AND 40 Arithmetic Shift Left ......................ASL 41 Arithmetic Shift Right......................ASR 42 Call Function ........................CALL 43 Non-Destructive Compare....................CMP 44 Complement Accumulator ....................CPL 45 Decrement.........................
  • Page 5 Contents Export .........................EXPORT 88 Conditional Source ..................IF, ELSE, ENDIF 89 Include Source File ....................INCLUDE 90 Prevent Code Compression of Data ..........LITERAL, .ENDLITERAL 91 Macro Definition....................MACRO, ENDM 92 Area Origin ........................ORG 93 Section for Dead-Code Elimination ..........SECTION, .ENDSECTION 94 Suspend/Resume Code Compressor ............OR F,0;...
  • Page 6 Contents ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...

  • Page 7: Introduction

    Please contact your local distributor if you are interested in purchasing a C Compiler for PSoC Designer. For more information about developing in C for the PSoC device, please read the PSoC Designer C Language Compiler Guide available at the Cypress web site at www.cypress.com.

  • Page 8: Support

    PSoC Consultants, TightLink Technical Support Email/Knowledge Base, and Application Support Technicians. Before utilizing the Cypress support services, know the version of PSoC Designer installed on your system. To quickly determine the version, build, or service pack of your current installation of PSoC Designer, click Help >...

  • Page 9: Revision History

    Introduction Table 1-3. Acronyms Acronym Description no operation CPU_PC register (program counter) power-on-reset random access memory register space read only memory CPU_SP register (stack pointer) SROM supervisory read only memory supervisory system call watchdog timer reset CPU_X register (index) XRES external reset zero flag Revision History...
  • Page 10 Introduction ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...

  • Page 11: M8C Microprocessor

    M8C Microprocessor This chapter covers internal M8C registers, address spaces, instruction summary and formats, and addressing modes for the M8C microprocessor. The M8C is a 4 MIPS 8-bit Harvard architecture microprocessor. Code selectable processor clock speeds from 93.7 kHz to 24 MHz allow the M8C to be tuned to a particular application’s performance and power requirements.

  • Page 12: Address Spaces

    M8C Microprocessor With the exception of the CPU_F register, the M8C internal registers are not accessible via an explicit register address. PSoC parts in the CY8C25xxx and CY8C26xxx device family do not have a readable CPU_F register. The OR F, expr and AND F, expr instructions must be used to set and clear CPU_F register bits.
  • Page 13 M8C Microprocessor DB[7:0] PAGE DA[7:0] ID[7:0] PC[15:0] Registers Bank 0 Page 0 SROM 256 Bytes 256 Bytes Page 1 Bank 1 256 Bytes 256 Bytes Flash LEGEND M x 64 Total number of Flash bocks in device Byte Blocks Total number of RAM pages minus 1 in device XIO: Register bank selection Page n...

  • Page 14: Instruction Set Summary

    M8C Microprocessor Instruction Set Summary The instruction set is summarized in both Table 2-2 Table 2-3 (in numeric and mnemonic order, respectively), and serves as a quick reference. Table 2-2. Instruction Set Summary Sorted Numerically by Opcode Instruction For- Flags Instruction Format Flags Instruction Format...
  • Page 15 M8C Microprocessor Table 2-3. Instruction Set Summary Sorted Alphabetically by Mnemonic Instruction Format Flags Instruction Format Flags Instruction Format Flags 09 4 ADC A, expr C, Z INC [expr] C, Z POP X 0A 6 ADC A, [expr] C, Z INC [X+expr] C, Z POP A...

  • Page 16: Instruction Formats

    M8C Microprocessor Instruction Formats The M8C has a total of seven instruction formats which use instruction lengths of one, two, and three bytes. All instruction bytes are fetched from the program memory (Flash), using an address and data bus that are independent from the address and data buses used for register and RAM access. While examples of instructions are given in this section, refer to the M8C Instruction Set chapter on page 37...

  • Page 17: Three-Byte Instructions

    M8C Microprocessor The first two-byte instruction format, shown in the first row of Table 2-5, is used by short jumps and calls: CALL, JMP, JACC, INDEX, JC, JNC, JNZ, JZ. This instruction format uses only four bits for the instruction opcode, leaving 12 bits to store the relative destination address in a two’s-complement form.

  • Page 18: Addressing Modes

    M8C Microprocessor Addressing Modes The M8C has ten addressing modes: “Source Immediate” on page ■ “Source Direct” on page ■ “Source Indexed” on page ■ “Destination Direct” on page ■ “Destination Indexed” on page ■ “Destination Direct Source Immediate” on page ■...

  • Page 19: Source Direct

    M8C Microprocessor 2.5.2 Source Direct For these instructions, the source address is stored in operand 1 of the instruction. During instruction execution, the address will be used to retrieve the source value from RAM or register address space. The result of these instructions is placed in either the M8C CPU_A or CPU_X register as indicated by the instruction’s opcode.

  • Page 20: Destination Direct

    M8C Microprocessor 2.5.4 Destination Direct For these instructions, the destination address is stored in the machine code of the instruction. The source for the operation is either the M8C CPU_A or CPU_X register as indicated by the instruction’s opcode. All instructions using the Destination Direct addressing mode are two bytes in length. Table 2-10.

  • Page 21: Destination Direct Source Immediate

    M8C Microprocessor 2.5.6 Destination Direct Source Immediate For these instructions, the destination address is stored in operand 1 of the instruction. The source value is stored in operand 2 of the instruction. All instructions using the Destination Direct Source Immediate addressing mode are three bytes in length. Table 2-12.

  • Page 22: Destination Direct Source Direct

    M8C Microprocessor 2.5.8 Destination Direct Source Direct Only one instruction uses this addressing mode. The destination address is stored in operand 1 of the instruction. The source address is stored in operand 2 of the instruction. The instruction using the Destination Direct Source Direct addressing mode is three bytes in length. Table 2-14.

  • Page 23: Destination Indirect Post Increment

    M8C Microprocessor 2.5.10 Destination Indirect Post Increment Only one instruction uses this addressing mode. The destination address stored in operand 1 is actually the address of a pointer. During instruction execution, the pointer’s current value is read to determine the destination address in RAM where the Accumulator’s value is stored. The pointer’s value is incremented, after the value is written to the destination address.
  • Page 24 M8C Microprocessor ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...

  • Page 25: Imagecraft Assembler

    ImageCraft Assembler This chapter details the information needed to use the ImageCraft Assembler. For information on command line usage of the ImageCraft Assembler, see the C Language Compiler User Guide (sec- tion 9.4 ImageCraft Assembler Arguments). For information on generating source code in PSoC Designer, see the PSoC Designer IDE Guide.

  • Page 26: Labels

    ImageCraft Assembler All user code is built from the components listed in Table 3-1 and complex conditional-assembly con- straints can be placed on a collection of source files. The text below has an example of each of the six basic components that will be discussed in detail in the following subsections. Line 1 is a com- ment line as indicated by the “//”...

  • Page 27: Mnemonics

    ImageCraft Assembler Global Labels. These are defined by the EXPORT assembler directive or by ending the label with two colons “::” rather than one. Global labels may be referenced from any source file in a project. The following example has two global labels. The EXPORT directive is used to make the SubFun label global, while two colons are used to make the MoreFun label global.

  • Page 28: Operands

    ImageCraft Assembler 3.1.3 Operands Operands are the arguments to instructions. The number of operands and the format they use are defined by the instruction being used. The operand format for each instruction is covered in the “Instruction Set Summary” on page Operands may take the form of constants, labels, dot operator, registers, RAM, or expressions.

  • Page 29: Comments

    ImageCraft Assembler Registers. These have two forms in PSoC devices. The first type are those that exist in the two banks of user-accessible registers. The second type are those that exist in the microcontroller. Table 3-3 contains examples for all types of register operands. Table 3-3.

  • Page 30: Directives

    ImageCraft Assembler 3.1.5 Directives An assembler directive is used to tell the ImageCraft Assembler to take some action during the assembly process. Directives are not understood by the M8C microcontroller. As such, directives allow the firmware writer to create code that is easier to maintain. See the Assembler Directives chapter on page 75 for more information on directives.
  • Page 31 ImageCraft Assembler 0x0000 in Flash. For the example below, only addresses 0x0000 through 0x002E of the Flash have assigned values according to the ROM file. Example ROM 80 5B 00 00 7E 00 00 00 File: 7E 00 00 00 7D 02 62 7E 7E 00 00 00 7D 01 EF 7E 91 73 90 FE 90 89 90 14 3D 7F 60 3A 5B 60 3E 7F...

  • Page 32: Intel® Hex File Format

    ImageCraft Assembler ® Intel HEX File Format The Intel HEX file created by the ImageCraft Assembler is used as a platform-independent way of distributing all of the information needed to program a PSoC microcontroller. In addition to the user data created by the Assembler, the HEX file also contains the protection settings for the project that will be used by the programmer.
  • Page 33 ImageCraft Assembler All HEX files created by the ImageCraft Assembler have the structure shown in Table 3-7. Each row in the table describes a record type used in the HEX file. Each record type conforms to the record definitions discussed previously. Table 3-7.

  • Page 34: Convention For Restoring Internal Registers

    Even though some of the APIs do preserve the CPU_X and CPU_A register, Cypress reserves the right to modify the API in future releases in such a manner as to modify the contents of the CPU_X and CPU_A registers.
  • Page 35 ImageCraft Assembler PSoC Designer automatically generates a certain amount of code for each new project. In this example, use the generated _main source file to hold regression tests, but do not add this file to the custom library. Also, do not add the generated boot.asm source file to the library. Essentially, all the files under the "Source Files"...
  • Page 36 ImageCraft Assembler The rules (for example, obj/%.o : %.asm project.mk and obj/%.o : %.c project.mk) in the local.dep file shown above are the same rules found in the master Makefile with one addition each. The addition in the redefined rules is to add each object (target) to a library called PSoC- ToolsLib.a.

  • Page 37: M8C Instruction Set

    M8C Instruction Set This chapter describes all M8C instructions in detail. The M8C supports a total of 256 instructions which are divided into 37 instruction types and arranged in alphabetical order according to the instruction types mnemonic. For each instruction the assembly code format will be illustrated as well as the operation performed by the instruction.

  • Page 38: Add With Carry

    M8C Instruction Set Add with Carry Computes the sum of the two operands plus the carry value from the Flag register. The first oper- and’s value is replaced by the computed sum. If the sum is greater than 255, the Carry Flag is set in the Flag register.

  • Page 39: Add Without Carry

    M8C Instruction Set Add without Carry Computes the sum of the two operands. The first operand’s value is replaced by the computed sum. If the sum is greater than 255, the Carry Flag is set in the Flag register. If the sum is zero, the Zero Flag is set in the Flag register.

  • Page 40: Bitwise And

    M8C Instruction Set Bitwise AND Computes the logical AND for each bit position using both arguments. The result of the logical AND is placed in the corresponding bit position for the first argument. The Carry Flag is only changed when the AND F, expr instruction is used. The CF will be set to the result of the logical AND of the CF at the beginning of instruction execution and the second argu- ment’s value at bit position 2 (i.e., F[2] and expr[2]).

  • Page 41: Arithmetic Shift Left

    M8C Instruction Set Arithmetic Shift Left Shifts all bits of the instruction’s argument one bit to the left. Bit 7 is loaded into the Carry Flag and bit 0 is loaded with a zero. Instructions Operation Opcode Cycles Bytes Mnemonic Argument ...

  • Page 42: Arithmetic Shift Right

    M8C Instruction Set Arithmetic Shift Right Shifts all bits of the instruction’s argument one bit to the right. Bit 7 remains the same while bit 0 is shifted into the Carry Flag. Instructions Operation Opcode Cycles Bytes Mnemonic Argument  ...

  • Page 43: Call Function

    M8C Instruction Set Call Function CALL Adds the signed argument to the current PC+2 value resulting in a new PC that determines the address of the first byte of the next instruction. The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the next instruction.

  • Page 44: Non-Destructive Compare

    M8C Instruction Set Non-Destructive Compare Subtracts the second argument from the first. If the difference is less than zero the Carry Flag is set. If the difference is 0 the Zero Flag is set. Neither operand’s value is destroyed by this instruction. Instructions Operation Opcode...

  • Page 45: Complement Accumulator

    M8C Instruction Set Complement Accumulator Computes the bitwise complement of the Accumulator and stores the result in the Accumulator. The Carry Flag is not affected but the Zero Flag will be set, if the result of the complement is ‘0’ (for example, the original value was 0xFF).

  • Page 46: Decrement

    M8C Instruction Set Decrement Subtracts one from the value of the argument and replaces the argument’s original value with the result. If the result is ‘-1’ (original value was zero) the Carry Flag is set. If the result is ‘0’ (original value was one) the Zero Flag is set.

  • Page 47: Halt

    M8C Instruction Set 4.10 Halt HALT Halts the execution of the processor. The processor will remain halted until a Power-On-Reset (POR), Watchdog Timer Reset (WDR), or external reset (XRES) event occurs. The POR, WDR, and XRES are all hardware resets that will cause a complete system reset, including the resetting of reg- isters to their power-on state.

  • Page 48: Increment

    M8C Instruction Set 4.11 Increment Adds one to the argument. The argument’s original value is replaced by the new value. If the value after the increment is 0x00, the Carry Flag and the Zero Flag will be set (original value must have been 0xFF).

  • Page 49: Relative Table Read

    M8C Instruction Set 4.12 Relative Table Read INDEX Places the contents of ROM at the location indicated by the sum of the Accumulator, the argument, and the current PC+2 into the Accumulator. This instruction has a 12-bit, two’s-complement offset address, relative to the current PC+2. The current PC value is defined as the PC value that corre- sponds to the ROM address of the first byte of the instruction.

  • Page 50: Jump Accumulator

    M8C Instruction Set 4.13 Jump Accumulator JACC Jump, unconditionally, to the address computed by the sum of the Accumulator, the 12-bit two’s- compliment argument, and the current PC+1. The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JACC instruction. The Accumulator is not affected by this instruction.

  • Page 51: Jump If Carry

    M8C Instruction Set 4.14 Jump if Carry If the Carry Flag is set, jump to the sum of the relative address argument and the current PC+1. The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JC instruction.

  • Page 52: Jump

    M8C Instruction Set 4.15 Jump Jump, unconditionally, to the address indicated by the sum of the argument and the current PC+1. The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JMP instruction.

  • Page 53: Jump If No Carry

    M8C Instruction Set 4.16 Jump if No Carry If the Carry Flag is not set, jump to the sum of the relative address argument and the current PC+1. The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JNC instruction.

  • Page 54: Jump If Not Zero

    M8C Instruction Set 4.17 Jump if Not Zero If the Zero Flag is not set, jump to the address indicated by the sum of the argument and the current PC+1. The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JNZ instruction.

  • Page 55: Jump If Zero

    M8C Instruction Set 4.18 Jump if Zero If the Zero Flag is set, jump to the address indicated by the sum of the argument and the current PC+1. The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JZ instruction.

  • Page 56: Long Call

    M8C Instruction Set 4.19 Long Call LCALL Replaces the PC value with the LCALL instruction’s argument. The new PC value determines the address of the first byte of the next instruction. Two pushes are used to store the Program Counter (current PC+3) on the stack. The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the instruc- tion.

  • Page 57: Long Jump

    M8C Instruction Set 4.20 Long Jump LJMP Jump, unconditionally, to the unsigned address indicated by the instruction’s argument. The LJMP instruction uses a three-byte instruction format to accommodate a full 16-bit argument. The first byte of the instruction is a full 8-bit opcode. Instructions Operation Opcode...

  • Page 58: Move

    M8C Instruction Set 4.21 Move Allows for a number of combinations of moves: immediate, direct, and indexed addressing are sup- ported. Instructions Operation Opcode Cycles Bytes Mnemonic Argument  X, SP 0x4F  A, expr 0x50  ram k   A, [expr] 0x51 ...

  • Page 59: Move Indirect, Post-Increment To Memory

    M8C Instruction Set 4.22 Move Indirect, Post-Increment to Memory A data pointer in RAM is used to move data between another RAM address and the Accumulator. The data pointer is incremented after the data transfer has completed. For PSoC microcontrollers with more than 256 bytes of RAM, special page pointers are used to allow the MVI instructions to access data in remote RAM pages.

  • Page 60: No Operation

    M8C Instruction Set 4.23 No Operation Performs no operation but consumes 4 CPU clock cycles. This is a one-byte instruction. Instructions Operation Opcode Cycles Bytes Mnemonic Argument None 0x40 Conditional Unaffected. Flags: Unaffected. ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...

  • Page 61: Bitwise Or

    M8C Instruction Set 4.24 Bitwise OR Computes the logical OR for each bit position using both arguments. The result of the logical OR is placed in the corresponding bit position for the first argument. The Carry Flag is only changed when the OR F, expr instruction is used. The Carry Flag will be set to the result of the logical OR of the Carry Flag at the beginning of instruction execution and the second argument’s value at bit position 2 (i.e., F[2] and expr[2]).

  • Page 62: Pop Stack Into Register

    M8C Instruction Set 4.25 Pop Stack into Register Removes the last byte placed on the stack and put it in the specified M8C register. The Stack Pointer is automatically decremented. The Zero Flag is set if the popped value is zero; otherwise, the Zero Flag is cleared.

  • Page 63: Push Register Onto Stack

    M8C Instruction Set 4.26 Push Register onto Stack PUSH Transfers the value from the specified M8C register to the top of the stack, as indicated by the value of the CPU_SP register (SP) at the start of the instruction. After placing the value on the stack, the SP is incremented.

  • Page 64: Return

    M8C Instruction Set 4.27 Return The last two bytes placed on the stack are used to change the PC (CPU_PC register). The lower 8 bits of the PC are popped off the stack first, followed by the SP being decremented by one. Next, the upper 8 bits of the PC are popped off the stack, followed by a decrement of the SP.

  • Page 65: Return From Interrupt

    M8C Instruction Set 4.28 Return from Interrupt RETI When the M8C takes an interrupt, three bytes are pushed onto the stack. One for CPU_F and two for the PC. When a RETI is executed, the last three bytes placed on the stack are used to change the CPU_F register and the CPU_PC register.

  • Page 66: Rotate Left Through Carry

    M8C Instruction Set 4.29 Rotate Left through Carry Shifts all bits of the instruction’s argument one bit to the left. Bit 0 is loaded with the Carry Flag. The most significant bit of the specified location is loaded into the Carry Flag. Instructions Operation Opcode...

  • Page 67: Absolute Table Read

    M8C Instruction Set 4.30 Absolute Table Read ROMX Moves any byte from ROM (Flash) into the Accumulator. The address of the byte to be retrieved is determined by the 16-bit value formed by the concatenation of the CPU_A and CPU_X registers. The CPU_A register is the most significant byte and the CPU_X register is the least significant byte of the address.

  • Page 68: Rotate Right Through Carry

    M8C Instruction Set 4.31 Rotate Right through Carry Shifts all bits of the instruction’s argument one bit to the right. The Carry Flag is loaded into the most significant bit of the argument. Bit 0 of the argument is loaded into the Carry Flag. Instructions Operation Opcode...

  • Page 69: Subtract With Borrow

    M8C Instruction Set 4.32 Subtract with Borrow Computes the difference of the two operands plus the carry value from the Flag register. The first operand’s value is replaced by the computed difference. If the difference is less than ‘0’ the Carry Flag is set in the Flag register.

  • Page 70: Subtract Without Borrow

    M8C Instruction Set 4.33 Subtract without Borrow Computes the difference of the two operands. The first operand’s value is replaced by the computed difference. If the difference is less than zero, the Carry Flag is set in the Flag register. If the differ- ence is zero, the Zero Flag is set in the Flag register;...

  • Page 71: Swap

    M8C Instruction Set 4.34 Swap SWAP Each argument is updated with the other argument’s value. The Zero Flag is set if the Accumulator is updated with zero, else the Zero Flag is cleared. The swap X, [expr] instruction does not affect either the Carry or Zero Flags.

  • Page 72: System Supervisor Call

    M8C Instruction Set 4.35 System Supervisor Call Provides the method for users to access pre-existing routines in the Supervisory ROM. The supervi- sory routines perform various system-related functions. The CPU_PC and CPU_F registers are pushed on the stack prior to the execution of the supervisory routine. All bits of the Flag register are cleared before any supervisory routine code is executed;...

  • Page 73: Test For Mask

    M8C Instruction Set 4.36 Test for Mask Calculates a bitwise AND with the value of argument one and argument two. Argument one’s value is not affected by the TST instruction. If the result of the AND is zero, the Zero Flag is set; otherwise, the Zero Flag is cleared.

  • Page 74: Bitwise Xor

    M8C Instruction Set 4.37 Bitwise XOR Computes the logical XOR for each bit position using both arguments. The result of the logical XOR is placed in the corresponding bit position for the argument. The Carry Flag is only changed when the XOR F, expr instruction is used. The CF will be set to the result of the logical XOR of the CF at the beginning of instruction execution and the second argu- ment’s value at bit position 2 (i.e., F[2] and expr[2]).

  • Page 75: Assembler Directives

    Assembler Directives This chapter covers all of the assembler directives currently supported by the ImageCraft Assembler. A description of each directive and its syntax will be given for each directive. ImageCraft Assembler directives are used to communicate with the ImageCraft Assembler and do not generate code. The directives allow a firmware developer to conditionally assemble source files, define symbolic equates for values, locate code or data at specific addresses, etc.

  • Page 76: Area

    Assembler Directives Area AREA Defines where code or data is located in Flash or RAM by the Linker. The Linker gathers all areas with the same name together from the source files, and either concatenates or overlays them, depending on the attributes specified. All areas with the same name must have the same attributes, even if they are used in different modules.

  • Page 77: Code Compressor And The Area Directive

    Assembler Directives 5.1.1 Code Compressor and the AREA Directive The Code Compressor looks for duplicate code within the “text” Area. The text area is the default area in which all C code is placed. Not Allowed Function X Function A Calls Function Y Function B...

  • Page 78: Null Terminated Ascii String

    Assembler Directives NULL Terminated ASCII String ASCIZ Stores a string of characters as ASCII values and appends a terminating NULL (00h) character. The string must start and end with quotation marks (""). The string is stored character by character in ASCII HEX format. The backslash character (\) is used in the string as an escape character.

  • Page 79: Ram Block In Bytes

    Assembler Directives RAM Block in Bytes Reserves blocks of RAM in bytes. The argument is an expression, specifying the size of the block, in bytes, to reserve. The AREA directive must be used to ensure the block of bytes will reside in the cor- rect memory location.

  • Page 80: Ram Block In Words

    Assembler Directives RAM Block in Words BLKW Reserves a block of RAM. The amount of RAM reserved is determined by the size argument to the directive. The units for the size argument is words (16 bits). PSoC Designer requires that the AREA bss be used for RAM variables. Directive Arguments BLKW...

  • Page 81: Define Byte

    Assembler Directives Define Byte Reserves bytes of ROM and assigns the specified values to the reserved bytes. This directive is useful for creating data tables in ROM. Arguments may be constants or labels. The length of the source line limits the number of arguments in a DB directive.

  • Page 82: Define Floating-Point Number

    Assembler Directives Define Floating-point Number Reserves four-byte pairs of ROM and assigns the specified values to each reserved pair. The format used is the IEEE-754 Single Format stored in big-endian format. This directive is useful for creating data tables in ROM. Arguments must be constants.

  • Page 83: Define Ascii String

    Assembler Directives Define ASCII String Stores a string of characters as ASCII values. The string must start and end with quotation marks (""). The string is stored character by character in ASCII HEX format. The backslash character (\) is used in the string as an escape character.

  • Page 84: Define Unicode String

    Assembler Directives Define UNICODE String Stores a string of characters as UNICODE values with little ENDIAN byte order. The string must start and end with quotation marks (""). The string is stored character by character in UNICODE format. Each character in the string is stored with the low byte followed by the high byte.

  • Page 85: Define Word, Big Endian Ordering

    Assembler Directives Define Word, Big Endian Ordering Reserves two-byte pairs of ROM and assigns the specified words to each reserved byte. This direc- tive is useful for creating tables in ROM. The arguments may be constants or labels. Only the length of the source line limits the number of arguments in a DW directive.

  • Page 86: Define Word, Little Endian Ordering

    Assembler Directives 5.10 Define Word, Little Endian Ordering Reserves two-byte pairs of ROM and assigns the specified words to each reserved byte, swapping the order of the upper and lower bytes. The arguments may be constants or labels. The length of the source line limits the number of argu- ments in a DWL directive.

  • Page 87: Equate Label

    Assembler Directives 5.11 Equate Label Assigns an integer value to a label. The label and operand are required for an EQU directive. The argument must be a constant or label or “.” (the current PC). Each EQU directive may have only one argument and, if a label is defined more than once, an assembly error will occur.

  • Page 88: Export

    Assembler Directives 5.12 Export EXPORT Designates that a label is global and can be referenced in another file. Otherwise, the label is not vis- ible to another file. Another way to export a label is to end the label definition with two colons (::) instead of one.

  • Page 89: Conditional Source

    Assembler Directives 5.13 Conditional Source IF, ELSE, ENDIF All source lines between the IF and ENDIF (or IF and ELSE) directives are assembled if the condi- tion is true. These statements can be nested. ELSE delineates a “not true” action for a previous IF directive. ENDIF finishes a section of conditional assembly that began with an IF directive.

  • Page 90: Include Source File

    Assembler Directives 5.14 Include Source File INCLUDE Used to add additional source files to the file being assembled. When an INCLUDE directive is encountered, the ImageCraft Assembler reads in the specified source file until either another INCLUDE directive is encountered or the end of file is reached. If additional INCLUDE directives are encountered, additional source files are read in.

  • Page 91: Prevent Code Compression Of Data

    Assembler Directives 5.15 Prevent Code Compression of Data .LITERAL, .ENDLITERAL Used to avoid code compression of the data defined between the .LITERAL and .ENDLITERAL directives. For the code compressor to function, all data defined in ROM with the ASCIZ, DB, DS, DSU, DW, or DWL directives must use this directive.
  • Page 92 Assembler Directives 5.16 Macro Definition MACRO, ENDM Used to specify the start and end of a macro definition. The lines of code defined between a MACRO directive and an ENDM directive are not directly assembled into the program. Instead, it forms a macro that can later be substituted into the code by a macro call.

  • Page 93: Area Origin

    Assembler Directives 5.17 Area Origin Allows the programmer to set the value of the Program/Data Counter during assembly. This is most often used to set the start of a table in conjunction with the define directives DB, DS, and DW. The ORG directive can only be used in areas with the ABS mode.

  • Page 94: Section For Dead-Code Elimination

    Assembler Directives 5.18 Section for Dead-Code Elimination .SECTION, .ENDSECTION Allows the removal of code specified between the .SECTION and .ENDSECTION directives. The .SECTION directive must be followed by an exported global label. If there is no call to the global label, the code will be eliminated and call offsets will be adjusted appropriately.
  • Page 95 Assembler Directives ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...
  • Page 96 Assembler Directives ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...

  • Page 97: Builds And Error Messages

    Builds and Error Messages This chapter briefly describes the PSoC Designer assemble and build process, linker operations, and errors you might encounter with your code. Assemble and Build Once you have added and modified assembly language source files, you must assemble the files and build the project.

  • Page 98: Code Compressor And Dead-Code Elimination Error Messages

    !X The compiler has failed an internal consistency check. This may be due to incorrect input or an internal error. Please report the information target == 0 || new_target at ..\optm8c.c(340) to "Cypress" at www.cypress.com/support. Designer\tools\make: *** [output/drc_test.rom] Error 1 Note To obtain support go to http://www.cypress.com/support/login.cfm...

  • Page 99: Reference Tables Appendix

    A. Reference Tables Appendix The tables in this appendix are intended to serve as a quick reference to the M8C assembler direc- tives. The tables are also found in the body of this guide. For detailed information on the instruction set and the assembler directives, refer to the Instruction Set Summary on page 14 and the...

  • Page 100: Assembler Directives Summary

    Assembler Directives Summary Table A-3. Assembler Directives Summary Symbol Directive AREA Area ASCIZ NULL Terminated ASCII String RAM Byte Block BLKW RAM Word Block Define Byte Define ASCII String Define UNICODE String Define Word Define Word With Little Endian Ordering ELSE Alternative Result of IF Directive ENDIF...

  • Page 101: Ascii Code Table

    ASCII Code Table Table A-4. ASCII Code Table Char Char Char Char NULL space ‘ “ & ‘ < > ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...

  • Page 102: Instruction Set Summary

    Instruction Set Summary Table A-5. Instruction Set Summary Sorted Numerically by Opcode Instruction For- Flags Instruction Format Flags Instruction Format Flags 00 15 1 SSC 2 OR [X+expr], A 2 MOV [expr], X 2 ADD A, expr C, Z 3 OR [expr], expr 1 MOV A, X 2 ADD A, [expr] C, Z...
  • Page 103 Table A-6. Instruction Set Summary Sorted Alphabetically by Mnemonic Instruction Format Flags Instruction Format Flags Instruction Format Flags 09 4 ADC A, expr C, Z INC [expr] C, Z POP X 0A 6 ADC A, [expr] C, Z INC [X+expr] C, Z POP A 0B 7...
  • Page 104 ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...
  • Page 105 Index complement accumulator instruction 45 components of assembly source file 25 absolute table read instruction 67 compressor and dead code error message ADD instruction 39 elimination 98 ADD SP,0 directive 94 conditional source directive 89 add with carry instruction 38 constants format table 99 add without carry instruction 39 conventions 8...
  • Page 106 Index ENDIF directive 89 ENDLITERAL directive 91 LCALL instruction 56 ENDM directive 92 library module, compiling file 34 ENDSECTION directive 94 linker EQU directive 87 operations 97 equate label directive 87 listing file format 30 errors 97 LITERAL directive 91 LJMP instruction 57 local labels 26 long call instruction 56...
  • Page 107 Index prevent code compression of data 91 TST instruction 73 product support 8 upgrades 8 PUSH instruction 63 upgrades 8 push register onto stack instruction 63 warnings 97 RAM block in bytes directive 79 RAM block in words directive 80 relative table read instruction 49 restoring internal registers 34 resume code compressor directive 94...
  • Page 108 Index ImageCraft Assembly Language Guide, Document # 001-44475 Rev. *B [+] Feedback...

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