Epson EPL-N2000 Service Manual page 157

Appendix
Table A-16 C207 MAIN Board CN5 (I/O Bus)
Pin Signal Name
1
PCLK
2
RST
3
GND
4
GND
5
GND
6
GND
7
DB0
8
DB1
9
DB2
10
DB3
11
DB4
12
DB5
13
DB6
14
DB7
15
AB0
16
AB1
17
AB2
18
AB3
19
AB4
20
CS
21
RD
22
WR
23
IREQ
24
NMI
25
DREQ
26
DTCT
27
+5V
28
+5V
29
+5V
30
+5V
31
TXD+
32
TXD-
33
RXD+
34
RXD-
35
DTR
36
CTS
37
NC
38
NC
39
LCD
40
SWRD
41~60
Not used
A-8
I/O
I
System clock for 85230-10
I/O
Reset signal
-
GND
-
GND
-
GND
-
GND
I/O
Bidirectional data bus 0
I/O
Bidirectional data bus 1
I/O
Bidirectional data bus 2
I/O
Bidirectional data bus 3
I/O
Bidirectional data bus 4
I/O
Bidirectional data bus 5
I/O
Bidirectional data bus 6
I/O
Bidirectional data bus 7
-
Address bus
-
Address bus
-
Address bus
-
Address bus
-
Address bus
-
Chip select signal
-
Read signal. Goes LOW with WR signal at reset.
-
Write signal. Goes LOW with RD signal at reset.
O
Interruption request signal
O
Non-maskable interrupt request signal
O
DMA request signal
O
Board detection signal
-
+5 V
-
+5 V
-
+5 V
-
+5 V
O
Not used
O
Not used
I
Not used
I
Not used
O
Not used
I
Not used
-
No connection
-
No connection
I
Not used
I
Not used
-
—
EPL-N2000 Service Manual
Description
Rev. A