Processor 11/12 - Clevo N150ZU Service Manual

Processor 3/12
5
VCCIO
D
CFG[0]: Stall reset sequence after PCU PLL
lock until de-asserted:
— 1 = (Default) Normal Operation; No
stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
CFG[2]: PCI Express* Static x16 Lane
Numbering Reversal.
C — 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
CFG[4]: eDP enable:
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
— 1 = (default) PEG Train immediately
following RESET# de assertion.
— 0 = PEG Wait for BIOS for training.
CFG[19:8]: Reserved configuration lanes.
B
A
5
4 3
R71
2018/6/27
*150_04
U25Q
CFG0 T4
CFG_0
*1K_04 R72 CFG0
R4
CFG_1
T3
CFG_2
CFG3 R3
CFG_3
CFG4 J4
CFG_4
1K_04 R432 CFG4 CFG5 M4
CFG_5
J3
CFG6
CFG_6
CFG7 M3
CFG_7
*1K_04 R431 CFG6 R2
CFG_8
*1K_04 R436 CFG5 N2
CFG_9
R1
CFG_10
N1
CFG_11
J2
CFG_12
L2
CFG_13
J1
CFG_14
L1
CFG_15
L3
CFG_16
N3
CFG_18
L4
CFG_17
N4
check ok CFG_19
R74 49.9_1%_04 CFG_RCOMP AB5
CFG_RCOMP
W4
R442 1.5K_04
1.05VA
ITP_PMODE
CG2
RSVD_8
CG1
RSVD_9
H4
RSVD_10
H3
RSVD_11
BV24
RSVD_12
BV25
RSVD_13
BK36
RSVD_18
BK35
RSVD_17
W3
RSVD_4
AM4
RSVD_5
AM3
RSVD_TP_7/RSVD/RSVD_TP_7
4 3
2
WHL QS/CFL/WHL_ES1_CNL U
F37
RSVD_TP_5
F34
RSVD_TP_6
CP36
IST_TRIG
CN36
RSVD_TP_12
BJ36
RSVD_TP_3/RSVD/RSVD_TP_3
BJ34
RSVD_TP_4/RSVD/RSVD_TP_4
BK34
TP_3
BR18
TP_4
BT9
RSVD_TP_8/RSVD/RSVD_TP_8
BT8
RSVD_TP_9/RSVD/RSVD_TP_9
BP8
RSVD_TP_10/RSVD/RSVD_TP_10
BP9
RSVD_TP_11/RSVD/RSVD_TP_11
CR4
RSVD_14
CP3
RSVD_15
CR3
RSVD_16
AT3
RSVD_TP_13/RSVD/RSVD_TP_13
AU3
RSVD_TP_1/RSVD/RSVD_TP_1
AN1
RSVD_2
AN2
RSVD_3
AN4
RSVD_6
AN3
RSVD_7
AL2
IST_TP_0/RSVD/IST_TP_0
AL1
IST_TP_1/RSVD/IST_TP_1
AL4
IST_TRIG_0/RSVD/IST_TRIG_0
AL3
IST_TRIG_1/RSVD/IST_TRIG_1
BP34
TP_2
BP36
VSS_1/TP/VSS_1
BP35
TP_1
CR35
RSVD_TP_2/RSVD/RSVD_TP_2
E1
SKTOCC# R427 10K_04
3.3VA
SKTOCC#
WHL_U_IP_CCG/BGA
20 of 20
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[04] WHL U D,Q/20 CFG [04] WHL U D,Q/20 CFG [04] WHL U D,Q/20 CFG
Size Size Size Document Number Document Number Document Number
6-71-N15Z0-D01 6-71-N15Z0-D01 6-71-N15Z0-D01
A3 A3 A3 N150ZU N150ZU N150ZU
Date: Date: Date: Wednesday, August 29, 2018 Wednesday, August 29, 2018 Wednesday, August 29, 2018
2
Schematic Diagrams
1
D
Sheet 4 of 46
C
Processor 3/12
B
A
Rev Rev Rev
D01 D01 D01
Sheet Sheet Sheet 4 4 4 of of of 46 46 46
1
Processor 3/12 B - 5