Ps8338B - Clevo N150ZU Service Manual

PS8338B

5
PS8338B_PEQ
R512
3 Levels Input:
L: Low
R513
H: High
M: VDD33/2, connect both
pull-up and pull-down resistors
PI0
R282
PS8338B_CFG0
R291 *4.7K_04
3.3VS
W/TBT
D
Chip operational mode configuration;
Internal pull down at ~150K , 3.3V
I/O.
L: Control switching mode (default)
H: Automatic switching mode
PS8338B_SW
R515 *4.7K_04
7 PS8338B_SW 3.3VS
W/TBT
Port switching control or priority configuration;
Internal pull down at ~150K , 3.3V I/O.
L: Port1 is selected or with higher priority (default)
H: Port2 is selected or with higher priority
L:mDP H:TBT
PS8338B
3,19 MUX_HPD
C
3.3VS
IN_CA_DET
C230 0.1u_10V_X5R_04
3,19 MDP_D0
W/TBT C420
IN_D0p
C229 0.1u_10V_X5R_04 0.1u_6.3V_X5R_02
3,19 MDP_D#0
W/TBT W/TBT IN_D0n
PS8338B_PEQ
IN_D1p
C228 0.1u_10V_X5R_04
3,19 MDP_D1
IN_D1n
W/TBT
C227 0.1u_10V_X5R_04
3,19 MDP_D#1
W/TBT IN_D2p
IN_D2n
PS8338B_PD
C226 0.1u_10V_X5R_04
3,19 MDP_D2
IN_D3p
W/TBT
IN_D3n
C225 0.1u_10V_X5R_04
3,19 MDP_D#2
W/TBT
PS8338B_SW
C224 0.1u_10V_X5R_04
3,19 MDP_D3
C241
W/TBT
C223 0.1u_10V_X5R_04
3,19 MDP_D#3
W/TBT 2.2u_6.3V_X5R_04
W/TBT
PD PIN:
L:Normal operation(default)
B
H:Chip power down
PS8338B_PD
R514 *0_04
7 PS8338B_PCH
W/TBT
From Intel
3,19 MDP_CTRLCLK
3,19 MDP_CTRLDATA
Separate DDC/AUX
From Intel
C240
3,19 MDP_AUX
C239
3,19 MDP_AUX#
A
5
4 3
3URJUDPPDEOH LQSXW HTXDOL]DWLRQ OHYHOV ,QWHUQDO SXOO GRZQ DW a .
*4.7K_04
3.3VS
W/TBT 3.3V I/O.
L: default, LEQ, compensate channel loss up to11.5dB @ HBR2
*4.7K_04
H: HEQ, compensate channel loss up to 14.5dB @ HBR2
W/TBT
M: LLEQ, compensate channel loss up to 8.5dB @ HBR2
*4.7K_04
3.3VS
W/TBT Automatic EQ disable; Internal pull down at
~150K , 3.3V IO
L: Automatic EQ enable (default)
H: Automatic EQ disable
$XWR WHVW HQDEOH ,QWHUQDO SXOO GRZQ DW a .
, 3.3V I/O.
L: Auto test disable & input offset cancellation enable
(default)
H: Auto test enable & input offset cancellation enable
M: Auto test disable & input offset cancellation disable
3.3VS
3.3VS
C419
0.01u_16V_X7R_04 C428
W/TBT 0.1u_6.3V_X5R_02
W/TBT
3 inch 0 via,
U10
2 inch 1
data lane not swap.
PI1_A
1 50
PI1/SCL_CTL OUT1_D0p
2 49
I2C_CTL_EN OUT1_D0n
3 48
OUT1_HPD
IN_HPD OUT1_HPD
4 47
IN_CA_DET OUT1_D1p
5 46
VDD33 OUT1_D1n
6 45
IN_D0p OUT1_D2p
7 44
IN_D0n OUT1_D2n
8 43
PEQ OUT1_CA_DET MDP_MODE
9 42
IN_D1p OUT1_D3p
10 PS8338B 41
IN_D1n OUT1_D3n
11 40
GND OUT2_D0p
12 39
IN_D2p OUT2_D0n
13 38
IN_D2n OUT2_HPD OUT2_HPD
14 37
PD OUT2_D1p
15 36
IN_D3p OUT2_D1n
16 35
IN_D3n OUT2_D2p
17 34
CEXT OUT2_D2n OUT2_CA_DET_A
18 33
SW OUT2_CA_DET
19 32
GND OUT2_D3p
20 31
REXT OUT2_D3n
R281
4.99K_1%_04
W/TBT
W/TBT
3.3VS 3.3VS
3.3VS
C267
C253
R315
0.1u_6.3V_X5R_02 0.01u_16V_X7R_04
W/TBT 100K_04
To TBT
W/TBT
W/TBT
OUT2_AUXn_SDA 20
OUT2_AUXp_SCL 20
R314
100K_04
W/TBT
0.1u_10V_X5R_04 W/TBT 3.3VS
0.1u_10V_X5R_04 W/TBT
R306
100K_04 To MDP CON
W/TBT
OUT1_AUXn_SDA
OUT1_AUXp_SCL
R305
100K_04
W/TBT
4 3
2
,
PC10 R294 *4.7K_04 W/TBT
3.3VS
R292 *4.7K_04 W/TBT
PC20 R309 *4.7K_04 W/TBT
3.3VS
R307
*4.7K_04 W/TBT
PC11 R295 *4.7K_04 W/TBT
3.3VS
R293
*4.7K_04 W/TBT
PC21 R310 *4.7K_04 W/TBT
3.3VS
R308
*4.7K_04 W/TBT
via (4 lane via),
OUT1_D0p 19
OUT1_D0n 19
19
OUT1_D1p 19
To mDP DIFF=100ohm,
OUT1_D1n 19
OUT1_D2p 19
OUT1_D2n 19
19
OUT1_D3p 19
OUT1_D3n 19
OUT2_D0p 20
OUT2_D0n 20
20
OUT2_D1p 20
OUT2_D1n 20
OUT2_D2p 20 DIFF=100ohm,
To TBT
OUT2_D2n 20
OUT2_D3p 20
OUT2_D3n 20
19
19
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[18] PS8338B [18] PS8338B [18] PS8338B
Size Size Size Document Number Document Number Document Number
A3 A3 A3 N150ZU N150ZU N150ZU
Date: Date: Date: Wednesday, August 29, 2018 Wednesday, August 29, 2018 Wednesday, August 29, 2018
2
Schematic Diagrams
1
D
Sheet 18 of 46
PS8338B
C
B
A
Rev Rev Rev
6-71-N15Z0-D01 6-71-N15Z0-D01 6-71-N15Z0-D01
D01 D01 D01
Sheet Sheet Sheet 18 18 18 of of of 46 46 46
1
PS8338B B - 19