Using External Files; Clock Netork Performance Optimization - Analog Devices AD9166-FMC-EBZ User Manual

UG-1698

USING EXTERNAL FILES

The DPGDownloader software allows users to import and use
files generated outside the tool. Perform the following steps to
import an external file:
1. Generate a file with the following criteria: text file signed
integer, one value per line, minimum value = −2
(for a 16-bit DAC, this is −(2
(bits − 1)
value = 2 − 1 (for a 16-bit DAC, this is (2
32,767), and file length divisible by 256.
2. Import the file on DPGDownloader by clicking Add Data
File (below the File menu).
3. Select the text file (see Figure 17).
4. Select and download this file like any other signal file. An
I/Q file must be generated for any of the complex data
modes.

CLOCK NETORK PERFORMANCE OPTIMIZATION

The user can measure the ADF4372
routing the ADF4372 output to J4 and away from the
CLK± pins, by looping the RFAUX8x output toward J4 as
shown in Figure 1. In this case, the
DAC clock.
Alternatively, the ADF4372 phase noise can be inferred directly
from the AD9166 output, as shown in Figure 16.
The on-board loop filter external to the
Type II, third-order low-pass filter. The user can customize and
optimize the filter by using ADIsimPLL.
The ADF4372 register settings generated by the AD9166
STARTUP WIZARD are typical, optimized for improved phase
noise performance at the output of the ADF4372. The user can
use the standalone ADF4372 tools (found in the zip file available
at www.analog.com/adf4372) to regenerate new
settings, and enter them into the register map view of the
ADF4372 by selecting ADF4372 from the DAC Clock Source
dropdown box (see Figure 4). To simplify configuration and
avoid entering commands manually into the register map one at
a time, an ACE macro can be used to play a sequence.
macros can play a sequence of SPI commands, inserting delays
to allow the PLL to lock where necessary.
(bits − 1)
− 1
15
− 1) = −32,767), maximum
15
− 1) =
performance directly by
AD9166
AD9166 does not receive a
ADF4372 is a standard
ADF4372
ACE
Figure 17. Choosing to Load an External File
Rev. 0 | Page 16 of 23
AD9166-FMC-EBZ
The ADF4372 phase frequency detector (PFD) spur level is
related to the PFD frequency. A lower PFD frequency can help
reduce the PFD spur, while it also narrows the loop bandwidth
and affects the PLL output phase noise. A higher PFD frequency
increases the loop bandwidth and may improve the output
phase noise of the PLL. Operating the
fractional-N mode necessarily results in fractional spurs and a
noticeably worse phase noise when compared to a similar
frequency that allows operating the PLL in integer mode.
Consult the ADF4372 data sheet for more details.
The PFD frequency typically used in the AD9166 STARTUP
WIZARD is 245.76 MHz, generated from a 122.88 MHz
VCXO, and multiplied 2× internally to the ADF4372. The user
can choose the PFD frequency according to the phase noise and
the PFD spur level requirements.
Optimal phase noise performance is achieved with a laboratory
grade, external clock source. A comparison of various clock
sources and the resulting phase noise measured at the
output is shown in Figure 16. Figure 16 compares different
external clock sources with the on-board ADF4372. In this case,
the AD9166 is clocked at 5898.24 MHz, a rate that is an integer
multiple of 122.88 MHz. The
NCO only mode.
0
Rohde & Schwarz SMA100B, UNIT 1
KEYSIGHT PSG
–20
Rohde & Schwarz SMA100B, UNIT 2
ON-BOARD ADF4372, REFERENCE = 122.88MHz VCXO
–40
–60
–80
–100
–120
–140
–160
–180
10 100 1k
OFFSET FREQUENCY (Hz)
Figure 16. AD9166
User Guide
ADF4372 PLL in
AD9166
AD9166 output is 900 MHz in
10k 100k 1M 10M 100M
Output Phase Noise