Silicon Laboratories C8051F330 Manual page 8

C8051F330/1/2/3/4/5
Figure 10.2. Power-On and VDD Monitor Reset Timing .......................................... 98
11. Flash Memory
Figure 11.1. Flash Program Memory Map.............................................................. 105
12. External RAM
13. Oscillators
Figure 13.1. Oscillator Diagram.............................................................................. 113
Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 119
14. Port Input/Output
Figure 14.1. Port I/O Functional Block Diagram ..................................................... 123
Figure 14.2. Port I/O Cell Block Diagram ............................................................... 124
Figure 14.3. Crossbar Priority Decoder with No Pins Skipped ............................... 125
Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 126
15. SMBus
Figure 15.1. SMBus Block Diagram ....................................................................... 135
Figure 15.2. Typical SMBus Configuration ............................................................. 136
Figure 15.3. SMBus Transaction ............................................................................ 137
Figure 15.4. Typical SMBus SCL Generation......................................................... 141
Figure 15.5. Typical Master Transmitter Sequence................................................ 147
Figure 15.6. Typical Master Receiver Sequence.................................................... 148
Figure 15.7. Typical Slave Receiver Sequence...................................................... 149
Figure 15.8. Typical Slave Transmitter Sequence.................................................. 150
16. UART0
Figure 16.1. UART0 Block Diagram ....................................................................... 153
Figure 16.2. UART0 Baud Rate Logic .................................................................... 154
Figure 16.3. UART Interconnect Diagram .............................................................. 155
Figure 16.4. 8-Bit UART Timing Diagram............................................................... 155
Figure 16.5. 9-Bit UART Timing Diagram............................................................... 156
Figure 16.6. UART Multi-Processor Mode Interconnect Diagram .......................... 157
17. Enhanced Serial Peripheral Interface (SPI0)
Figure 17.1. SPI Block Diagram ............................................................................. 163
Figure 17.2. Multiple-Master Mode Connection Diagram ....................................... 166
Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode
Connection Diagram166
Figure 17.4. 4-Wire Single Master Mode and 4-Wire Slave Mode
Connection Diagram166
Figure 17.5. Master Mode Data/Clock Timing ........................................................ 168
Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 169
Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 169
Figure 17.8. SPI Master Timing (CKPHA = 0)........................................................ 173
Figure 17.9. SPI Master Timing (CKPHA = 1)........................................................ 173
Figure 17.10. SPI Slave Timing (CKPHA = 0)........................................................ 174
Figure 17.11. SPI Slave Timing (CKPHA = 1)........................................................ 174
18. Timers
Figure 18.1. T0 Mode 0 Block Diagram.................................................................. 178
Figure 18.2. T0 Mode 2 Block Diagram.................................................................. 179
8 Rev. 1.7