Silicon Laboratories C8051F333 Manuals

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Silicon Laboratories C8051F333 Manual

Silicon Laboratories C8051F333 Manual (214 pages)

Mixed-Signal ISP Flash MCU

Brand: Silicon Laboratories | Category: Single board computers | Size: 2 MB

Table of Contents

Table of Contents
3
1 System Overview

17
- Table 1.1. Product Selection Guide
  18
2 Absolute Maximum Ratings

31
- Table 2.1. Absolute Maximum Ratings
  31
3 Global Electrical Characteristics

32
- Table 3.1. Global Electrical Characteristics
  32
- Table 3.2. Index to Electrical Characteristics Tables
  34
4 Pinout and Package Definitions

35
5 Bit ADC (ADC0, C8051F330/2/4 Only)

41
6 Bit Current Mode DAC (IDA0, C8051F330 Only)

57
7 Voltage Reference (C8051F330/2/4 Only)

61
- Figure 7.1. Voltage Reference Functional Block Diagram
  61
- Table 7.1. Voltage Reference Electrical Characteristics
  63
8 Comparator0

65
9 Microcontroller

71
- Figure 9.1. CIP-51 Block Diagram
  71
  - Instruction Set
    72
    
    Instruction and CPU Timing
    72
    
    MOVX Instruction and Program Memory
    72
    
    Table 9.1. CIP-51 Instruction Set Summary
    73
  - Memory Organization
    76
    
    Program Memory
    77
    
    Figure 9.2. Memory Map
    77
    
    Data Memory
    78
    
    General Purpose Registers
    78
    
    Bit Addressable Locations
    78
    
    Stack
    78
    
    Special Function Registers
    79
    
    Table 9.2. Special Function Register (SFR) Memory Map
    79
    
    Table 9.3. Special Function Registers
    80
    
    Register Descriptions
    83
  - Interrupt Handler
    85
    
    MCU Interrupt Sources and Vectors
    86
    
    External Interrupts
    87
    
    Interrupt Priorities
    87
    
    Interrupt Latency
    87
    
    Table 9.4. Interrupt Summary
    88
    
    Interrupt Register Descriptions
    89
  - Power Management Modes
    94
    
    Idle Mode
    94
    
    Stop Mode
    95
10 Reset Sources

97
- Figure 10.1. Reset Sources
  97
  - Power-On Reset
    98
  - Power-Fail Reset/VDD Monitor
    98
  - Figure 10.2. Power-On and VDD Monitor Reset Timing
    98
  - External Reset
    99
  - Missing Clock Detector Reset
    99
  - Comparator0 Reset
    100
  - PCA Watchdog Timer Reset
    100
  - Flash Error Reset
    100
  - Software Reset
    100
  - Table 10.1. Reset Electrical Characteristics
    102
11 Flash Memory

103
- Programming the Flash Memory
  103
  - Flash Lock and Key Functions
    103
  - Flash Erase Procedure
    103
  - Flash Write Procedure
    104
- Non-Volatile Data Storage
  104
- Table 11.1. Flash Electrical Characteristics
  104
- Security Options
  105
- Figure 11.1. Flash Program Memory Map
  105
- Table 11.2. Flash Security Summary
  106
- Flash Write and Erase Guidelines
  107
  - VDD Maintenance and the VDD Monitor
    107
  - PSWE Maintenance
    107
  - System Clock
    108
12 External RAM

111
13 Oscillators

113
14 Port Input/Output

123
- Figure 14.1. Port I/O Functional Block Diagram
  123
15 Smbus

135
- Figure 15.1. Smbus Block Diagram
  135
  - Supporting Documents
    136
  - Smbus Configuration
    136
  - Smbus Operation
    136
    
    Figure 15.2. Typical Smbus Configuration
    136
    
    Arbitration
    137
    
    Figure 15.3. Smbus Transaction
    137
    
    Clock Low Extension
    138
    
    SCL High (Smbus Free) Timeout
    138
    
    SCL Low Timeout
    138
  - Using the Smbus
    138
    
    Smbus Configuration Register
    140
    
    Table 15.1. Smbus Clock Source Selection
    140
    
    Figure 15.4. Typical Smbus SCL Generation
    141
    
    Table 15.2. Minimum SDA Setup and Hold Times
    141
    
    SMB0CN Control Register
    143
    
    Table 15.3. Sources for Hardware Changes to SMB0CN
    145
    
    Data Register
    146
  - Smbus Transfer Modes
    146
    
    Master Transmitter Mode
    146
    
    Figure 15.5. Typical Master Transmitter Sequence
    147
    
    Master Receiver Mode
    148
    
    Figure 15.6. Typical Master Receiver Sequence
    148
    
    Slave Receiver Mode
    149
    
    Figure 15.7. Typical Slave Receiver Sequence
    149
    
    Slave Transmitter Mode
    150
  - Smbus Status Decoding
    150
  - Figure 15.8. Typical Slave Transmitter Sequence
    150
  - Table 15.4. Smbus Status Decoding
    151
16 Uart0

153
- Figure 16.1. UART0 Block Diagram
  153
17 Enhanced Serial Peripheral Interface (SPI0)

163
- Figure 17.1. SPI Block Diagram
  163
18 Timers

177
- Timer 0 and Timer 1
  177
- Timer 2
  185
- Timer 3
  189
19 Programmable Counter Array

193
- Figure 19.1. PCA Block Diagram
  193
20 C2 Interface

209
- C2 Interface Registers
  209
- C2 Pin Sharing
  211
- Figure 20.1. Typical C2 Pin Sharing
  211

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