Microcontroller; Figure 9.1. Cip-51 Block Diagram - Silicon Laboratories C8051F330 Manual

9. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in
in Section 16), an Enhanced SPI (see description in
Special Function Register (SFR) address space
tion 14). The CIP-51 also includes on-chip debug hardware (see description in
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Section 18), an enhanced full-duplex UART (see description
Section
(Section
DATA BUS
ACCUMULATOR
TMP1 TMP2
PSW
ALU
DATA BUS
BUFFER
D8
D8
DATA POINTER
D8
PC INCREMENTER
D8
PROGRAM COUNTER (PC)
PRGM. ADDRESS REG.
A16
PIPELINE
D8
CONTROL
RESET
LOGIC
CLOCK
D8
STOP
POWER CONTROL
D8
IDLE
REGISTER

Figure 9.1. CIP-51 Block Diagram

Rev. 1.7
C8051F330/1/2/3/4/5
17), 256 bytes of internal RAM, 128 byte
9.2.6), and 17 Port I/O (see description in
Section
- 256 Bytes of Internal RAM
- 17 Port I/O
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
B REGISTER STACK POINTER
SRAM
SRAM
ADDRESS
(256 X 8)
REGISTER
SFR_ADDRESS
SFR_CONTROL
SFR
BUS
SFR_WRITE_DATA
INTERFACE
SFR_READ_DATA
MEM_ADDRESS
MEM_CONTROL
MEMORY
MEM_WRITE_DATA
INTERFACE
MEM_READ_DATA
SYSTEM_IRQs
INTERRUPT
INTERFACE
EMULATION_IRQ
Sec-
20), and interfaces
71