Spi Special Function Registers; Figure 17.6. Slave Mode Data/Clock Timing (Ckpha = 0); Figure 17.7. Slave Mode Data/Clock Timing (Ckpha = 1) - Silicon Laboratories C8051F330 Manual

SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MISO
NSS (4-Wire Mode)

Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0)

SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MISO
NSS (4-Wire Mode)

Figure 17.7. Slave Mode Data/Clock Timing (CKPHA = 1)

17.6. SPI Special Function Registers

SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
MSB Bit 6 Bit 5
MSB Bit 6 Bit 5
MSB Bit 6 Bit 5
MSB Bit 6 Bit 5
C8051F330/1/2/3/4/5
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
Bit 4 Bit 3 Bit 2
Rev. 1.7
Bit 1 Bit 0
Bit 1 Bit 0
Bit 1 Bit 0
Bit 1 Bit 0
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