Table 17.1. Spi Slave Timing Parameters - Silicon Laboratories C8051F330 Manual

Parameter
*
Master Mode Timing (See Figure 17.8 and Figure 17.9)
T
SCK High Time
MCKH
T
SCK Low Time
MCKL
T
MISO Valid to SCK Shift Edge
MIS
T
SCK Shift Edge to MISO Change
MIH
*
Slave Mode Timing (See Figure 17.10 and Figure 17.11)
T
NSS Falling to First SCK Edge
SE
T
Last SCK Edge to NSS Rising
SD
T
NSS Falling to MISO Valid
SEZ
T
NSS Rising to MISO High-Z
SDZ
T
SCK High Time
CKH
T
SCK Low Time
CKL
T
MOSI Valid to SCK Sample Edge
SIS
T
SCK Sample Edge to MOSI Change
SIH
T
SCK Shift Edge to MISO Change
SOH
Last SCK Edge to MISO Change
T
SLH
(CKPHA = 1 ONLY)
*Note: T is equal to one period of the device system clock (SYSCLK).
SYSCLK

Table 17.1. SPI Slave Timing Parameters

Description
C8051F330/1/2/3/4/5
Min
1 x T
SYSCLK
1 x T
SYSCLK
1 x T + 20
SYSCLK
0
2 x T
SYSCLK
2 x T
SYSCLK
—
—
5 x T
SYSCLK
5 x T
SYSCLK
2 x T
SYSCLK
2 x T
SYSCLK
—
6 x T
SYSCLK
Rev. 1.7
Max Units
— ns
— ns
— ns
— ns
— ns
— ns
4 x T ns
SYSCLK
4 x T ns
SYSCLK
— ns
— ns
— ns
— ns
4 x T ns
SYSCLK
8 x T ns
SYSCLK
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