Silicon Laboratories C8051F330 Manual
Silicon Laboratories C8051F330 Manual

Silicon Laboratories C8051F330 Manual

Mixed-signal isp flash mcu
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Analog Peripherals
-
10-Bit ADC ('F330/2/4 only)
Up to 200 ksps
Up to 16 external single-ended or differential inputs
VREF from internal VREF, external pin or V
Internal or external start of conversion source
Built-in temperature sensor
-
10-Bit Current Output DAC ('F330 only)
-
Comparator
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (0.4 µA)
On-Chip Debug
-
On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
-
Provides breakpoints, single stepping,
inspect/modify memory and registers
-
Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-
Low cost, complete development kit
Supply Voltage 2.7 to 3.6 V
-
Typical operating current: 6.4 mA at 25 MHz;
-
Typical stop mode current: 0.1 µA
Temperature Range: –40 to +85 °C
Rev. 1.7 12/10
DD
9 µA at 32 kHz
ANALOG
PERIPHERALS
10-bit
A
10-bit
Current
M
200 ksps
U
ADC
X
'F330 only
+
TEMP
SENSOR
-
VOLTAGE
'F330/2/4 only
COMPARATOR
24.5 MHz PRECISION
INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
2/4/8 kB
8051 CPU
ISP FLASH
(25 MIPS)
FLEXIBLE
INTERRUPTS
CIRCUITRY
Copyright © 2010 by Silicon Laboratories
C8051F330/1/2/3/4/5
Mixed-Signal ISP Flash MCU
High Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-
Up to 25 MIPS throughput with 25 MHz clock
-
Expanded interrupt handler
Memory
-
768 bytes internal data RAM (256 + 512)
-
8 kB ('F330/1), 4 kB ('F332/3), or 2 kB ('F334/5)
Flash; In-system programmable in 512-byte Sec-
tors—512 bytes are reserved in the 8 kB devices
Digital Peripherals
-
17 Port I/O; All 5 V tolerant with high sink current
-
Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
-
Four general purpose 16-bit counter/timers
-
16-Bit programmable counter array (PCA) with three
capture/compare modules
-
Real time clock mode using PCA or timer and exter-
nal clock source
Clock Sources
-
Two internal oscillators:
24.5 MHz with ±2% accuracy supports crystal-less
UART operation
80/40/20/10 kHz low frequency, low power
-
External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
-
Can switch between clock sources on-the-fly; useful
in power saving modes
20-Pin QFN Package
DIGITAL I/O
UART
SMBus
SPI
DAC
PCA
Timer 0
Timer 1
Timer 2
Timer 3
LOW FREQUENCY INTERNAL
OSCILLATOR
768 B SRAM
DEBUG
POR
Port 0
Port 1
P2.0
WDT
C8051F330/1/2/3/4/5

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Summary of Contents for Silicon Laboratories C8051F330

  • Page 1 ‘F330/2/4 only COMPARATOR 24.5 MHz PRECISION LOW FREQUENCY INTERNAL INTERNAL OSCILLATOR OSCILLATOR HIGH-SPEED CONTROLLER CORE 2/4/8 kB 8051 CPU 768 B SRAM ISP FLASH (25 MIPS) FLEXIBLE DEBUG INTERRUPTS CIRCUITRY Rev. 1.7 12/10 Copyright © 2010 by Silicon Laboratories C8051F330/1/2/3/4/5...
  • Page 2 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 3: Table Of Contents

    5.4. Programmable Window Detector ..............51 5.4.1. Window Detector In Single-Ended Mode ..........53 5.4.2. Window Detector In Differential Mode............54 6. 10-Bit Current Mode DAC (IDA0, C8051F330 only)..........57 6.1. IDA0 Output Scheduling ................... 57 6.1.1. Update Output On-Demand ..............57 6.1.2.
  • Page 4 C8051F330/1/2/3/4/5 9.2.5. Stack ....................... 78 9.2.6. Special Function Registers............... 79 9.2.7. Register Descriptions ................83 9.3. Interrupt Handler ....................85 9.3.1. MCU Interrupt Sources and Vectors ............86 9.3.2. External Interrupts ..................87 9.3.3. Interrupt Priorities ..................87 9.3.4. Interrupt Latency ..................87 9.3.5.
  • Page 5 C8051F330/1/2/3/4/5 14.3.General Purpose Port I/O ................129 15. SMBus ........................135 15.1.Supporting Documents ................... 136 15.2.SMBus Configuration..................136 15.3.SMBus Operation ................... 136 15.3.1.Arbitration....................137 15.3.2.Clock Low Extension................138 15.3.3.SCL Low Timeout................... 138 15.3.4.SCL High (SMBus Free) Timeout ............138 15.4.Using the SMBus.................... 138 15.4.1.SMBus Configuration Register...............
  • Page 6 C8051F330/1/2/3/4/5 18.2.2.8-bit Timers with Auto-Reload..............186 18.3.Timer 3 ......................189 18.3.1.16-bit Timer with Auto-Reload..............189 18.3.2.8-bit Timers with Auto-Reload..............190 19. Programmable Counter Array ................193 19.1.PCA Counter/Timer ..................194 19.2.Capture/Compare Modules ................195 19.2.1.Edge-triggered Capture Mode..............196 19.2.2.Software Timer (Compare) Mode............197 19.2.3.High-Speed Output Mode ..............
  • Page 7 Figure 5.7. ADC Window Compare Example: Right-Justified Differential Data ..54 Figure 5.8. ADC Window Compare Example: Left-Justified Differential Data ..54 6. 10-Bit Current Mode DAC (IDA0, C8051F330 only) Figure 6.1. IDA0 Functional Block Diagram............. 57 Figure 6.2. IDA0 Data Word Mapping..............58 7.
  • Page 8 C8051F330/1/2/3/4/5 Figure 10.2. Power-On and VDD Monitor Reset Timing .......... 98 11. Flash Memory Figure 11.1. Flash Program Memory Map.............. 105 12. External RAM 13. Oscillators Figure 13.1. Oscillator Diagram................113 Figure 13.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram . 119 14.
  • Page 9 C8051F330/1/2/3/4/5 Figure 18.3. T0 Mode 3 Block Diagram..............180 Figure 18.4. Timer 2 16-Bit Mode Block Diagram ..........185 Figure 18.5. Timer 2 8-Bit Mode Block Diagram ............ 186 Figure 18.6. Timer 3 16-Bit Mode Block Diagram ..........189 Figure 18.7. Timer 3 8-Bit Mode Block Diagram ............ 190 19.
  • Page 10 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 11 Table 3.1. Global Electrical Characteristics ............. 32 Table 3.2. Index to Electrical Characteristics Tables..........34 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5........... 35 Table 4.2. QFN-20 Package Dimensions ..............38 Table 4.3. QFN-20 PCB Land Pattern Dimesions ........... 39 5.
  • Page 12 C8051F330/1/2/3/4/5 Table 16.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz Oscillator .............. 160 Table 16.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator ............161 Table 16.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ............
  • Page 13 C8051F330/1/2/3/4/5 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select ....47 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select ....48 SFR Definition 5.3.
  • Page 14 C8051F330/1/2/3/4/5 SFR Definition 14.4. P0MDIN: Port0 Input Mode ......130 SFR Definition 14.5. P0MDOUT: Port0 Output Mode ......131 SFR Definition 14.6.
  • Page 15 C8051F330/1/2/3/4/5 C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control ... . 210 C2 Register Definition 20.5. FPDAT: C2 Flash Programming Data ....210...
  • Page 16 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 17: System Overview

    Each device is specified for 2.7 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F330/1/2/3/4/5 are available in 20-pin QFN packages (also referred to as MLP or MLF packages). Lead-free (RoHS compliant) packages are also available.
  • Page 18: Table 1.1. Product Selection Guide

    C8051F330/1/2/3/4/5 Table 1.1. Product Selection Guide             C8051F330-GM 25 QFN-20         C8051F331-GM 25 — — — — QFN-20    ...
  • Page 19: Figure 1.1. C8051F330 Block Diagram

    P1.7 Oscillator 80 kHz VREF Internal Oscillator 10-bit VREF Temp 10-bit AIN0-AIN15 200ksps Port 2 P2.0/C2D Latch Figure 1.1. C8051F330 Block Diagram Port 0 P0.0 Latch P0.1 UART P0.2/XTAL1 Timer 0, P0.3/XTAL2 1, 2, 3 Analog/Digital P0.4/TX Power 3-Chnl P0.5/RX...
  • Page 20: Figure 1.3. C8051F332 Block Diagram

    C8051F330/1/2/3/4/5 Port 0 P0.0/VREF Latch P0.1 UART P0.2/XTAL1 Timer 0, P0.3/XTAL2 1, 2, 3 Analog/Digital P0.4/TX Power 3-Chnl P0.5/RX PCA/ 4 kB P0.6/CNVST FLASH SMBus P0.7 Debug HW 256 byte P1.0 Reset SRAM /RST/C2CK Port 1 P1.1 Latch 512 byte Brown- P1.2...
  • Page 21: Figure 1.5. C8051F334 Block Diagram

    C8051F330/1/2/3/4/5 Port 0 P0.0/VREF Latch P0.1 UART P0.2/XTAL1 Timer 0, P0.3/XTAL2 1, 2, 3 Analog/Digital P0.4/TX Power 3-Chnl P0.5/RX PCA/ 2 kB P0.6/CNVST FLASH SMBus P0.7 Debug HW 256 byte P1.0 Reset SRAM /RST/C2CK Port 1 P1.1 Latch 512 byte Brown- P1.2...
  • Page 22: Microcontroller Core

    CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F330/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,...
  • Page 23: Additional Features

    C8051F330/1/2/3/4/5 1.1.3. Additional Features The C8051F330/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and periph- erals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing numerous analog and digital peripherals to interrupt the controller.
  • Page 24: On-Chip Memory

    C8051F330/1/2/3/4/5 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing.
  • Page 25: On-Chip Debug Circuitry

    The C8051F330DK development kit provides all the hardware and software necessary to develop applica- tion code and perform in-circuit debugging with the C8051F330/1/2/3/4/5 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and a debug adapter. It also has a target application board with the associated MCU installed and prototyping area, plus the required cables, and wall-mount power supply.
  • Page 26: Programmable Digital I/O And Crossbar

    C8051F330/1/2/3/4/5 devices include 17 I/O pins (two byte-wide Ports and one 1-bit-wide Port). The C8051F330/1/2/3/4/5 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be config- ured for push-pull or open-drain output.
  • Page 27: Programmable Counter Array

    C8051F330/1/2/3/4/5 1.6. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur- pose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with three program- mable capture/compare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8.
  • Page 28: 10-Bit Analog To Digital Converter

    10-Bit Analog to Digital Converter The C8051F330/2/4 devices include an on-chip 10-bit SAR ADC with a 16-channel differential input multi- plexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL and DNL of ±1 LSB.
  • Page 29: Comparators

    1.8. Comparators C8051F330/1/2/3/4/5 devices include an on-chip voltage comparator that is enabled/disabled and config- ured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchro- nous) output.
  • Page 30: 10-Bit Current Output Dac

    1.9. 10-bit Current Output DAC The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDA0). The maximum current output of the IDA0 can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA. IDA0 features a flexible output update mechanism which allows for seamless full-scale changes and sup- ports jitter-free updates for waveform generation.
  • Page 31: Absolute Maximum Ratings

    C8051F330/1/2/3/4/5 Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Conditions Units Ambient temperature under bias –55 — °C Storage Temperature –65 — °C Voltage on any Port I/O Pin or RST with –0.3 — respect to GND Voltage on V with respect to GND –0.3...
  • Page 32: Global Electrical Characteristics

    C8051F330/1/2/3/4/5 Global Electrical Characteristics Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Units Digital Supply Voltage Digital Supply RAM Data — — Retention Voltage — SYSCLK (System Clock) (Note 2) (SYSCLK High Time) —...
  • Page 33 C8051F330/1/2/3/4/5 Table 3.1. Global Electrical Characteristics –40 to +85 °C, 25 MHz system clock unless otherwise specified. Parameter Conditions Units Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash) (Note 3) = 3.6 V, F = 25 MHz —...
  • Page 34: Table 3.2. Index To Electrical Characteristics Tables

    C8051F330/1/2/3/4/5 Table 3.2. Index to Electrical Characteristics Tables Peripheral Electrical Characteristics Page No. ADC0 Electrical Characteristics IDAC Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Reset Electrical Characteristics Flash Electrical Characteristics Internal Oscillator Electrical Characteristics Port I/O DC Electrical Characteristics...
  • Page 35: Pinout And Package Definitions

    C8051F330/1/2/3/4/5 Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5 Name ‘F330/1/2/ Type Description ’F330-GP 3/4/5-GM Power Supply Voltage. Ground. RST/ D I/O Device Reset. Open-drain output of internal POR or V monitor. An external source can initiate a system reset by driving this pin low for at least 10 µs.
  • Page 36 C8051F330/1/2/3/4/5 Table 4.1. Pin Definitions for the C8051F330/1/2/3/4/5 (Continued) Name ‘F330/1/2/ Type Description ’F330-GP 3/4/5-GM P0.6/ D I/O or Port 0.6. See Section 14 for a complete description. A In CNVSTR D In ADC0 External Convert Start or IDA0 Update Source Input.
  • Page 37: Figure 4.1. Qfn-20 Pinout Diagram (Top View)

    C8051F330/1/2/3/4/5 P0.0 P0.6 P0.7 C8051F330/1/2/3/4/5-GM P1.0 Top View /RST/C2CK P1.1 P2.0/C2D P1.2 Figure 4.1. QFN-20 Pinout Diagram (Top View) Rev. 1.7...
  • Page 38: Table 4.2. Qfn-20 Package Dimensions

    C8051F330/1/2/3/4/5 Figure 4.2. QFN-20 Package Drawing Table 4.2. QFN-20 Package Dimensions Dimension Dimension 0.80 0.90 1.00 0.45 0.55 0.65 0.00 0.02 0.05 0.00 — 0.15 0.18 0.23 0.30 — — 0.15 4.00 BSC. — — 0.10 2.00 2.15 2.25 —...
  • Page 39: Table 4.3. Qfn-20 Pcb Land Pattern Dimesions

    C8051F330/1/2/3/4/5 Figure 4.3. QFN-20 Recommended PCB Land Pattern Table 4.3. QFN-20 PCB Land Pattern Dimesions Dimension Dimension 3.70 2.15 2.25 3.70 0.90 1.00 0.50 2.15 2.25 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted.
  • Page 40 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 41: Bit Adc (Adc0, C8051F330/2/4 Only)

    C8051F330/1/2/3/4/5 10-Bit ADC (ADC0, C8051F330/2/4 only) The ADC0 subsystem for the C8051F330/2/4 consists of two analog multiplexers (referred to collectively as AMUX0) with 16 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5.1.
  • Page 42: Temperature Sensor

    C8051F330/1/2/3/4/5 measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justified and left- justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’. Input Voltage Right-Justified ADC0H:ADC0L Left-Justified ADC0H:ADC0L (AD0LJST = 0)
  • Page 43: Modes Of Operation

    C8051F330/1/2/3/4/5 (Volts) 1.000 0.900 0.800 = 2.86(TEMP ) + 776 mV TEMP 0.700 0.600 0.500 (Celsius) Figure 5.2. Typical Temperature Sensor Transfer Function 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤...
  • Page 44: Starting A Conversion

    C8051F330/1/2/3/4/5 5.3.1. Starting a Conversion A conversion can be initiated in one of six ways, depending on the programmed states of the ADC0 Start of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol- lowing: 1.
  • Page 45: Tracking Modes

    C8051F330/1/2/3/4/5 5.3.2. Tracking Modes Each ADC0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. The minimum tracking time is given in Table 5.1. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode.
  • Page 46: Settling Time Requirements

    C8051F330/1/2/3/4/5 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accu- racy required for the conversion.
  • Page 47 C8051F330/1/2/3/4/5 SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select Reset Value AMX0P4 AMX0P3 AMX0P2 AMX0P1 AMX0P0 00011111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBB Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection AMX0P4–0...
  • Page 48 C8051F330/1/2/3/4/5 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select Reset Value AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00011111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBA Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0N4–0: AMUX0 Negative Input Selection.
  • Page 49 C8051F330/1/2/3/4/5 SFR Definition 5.3. ADC0CF: ADC0 Configuration Reset Value AD0SC4 AD0SC3 AD0SC2 AD0SC1 AD0SC0 AD0LJST 11111000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xBC Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4–0.
  • Page 50 C8051F330/1/2/3/4/5 SFR Definition 5.6. ADC0CN: ADC0 Control Reset Value AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE8 (bit addressable) Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown.
  • Page 51: Programmable Window Detector

    C8051F330/1/2/3/4/5 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times.
  • Page 52 C8051F330/1/2/3/4/5 SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC6 Bits7–0: High byte of ADC0 Less-Than Data Word SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte...
  • Page 53: Window Detector In Single-Ended Mode

    C8051F330/1/2/3/4/5 5.4.1. Window Detector In Single-Ended Mode Figure 5.5 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value.
  • Page 54: Window Detector In Differential Mode

    C8051F330/1/2/3/4/5 5.4.2. Window Detector In Differential Mode Figure 5.7 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (–1d). In differential mode, the measurable voltage between the input pins is between –VREF and VREF x (511/512). Output codes are represented as 10-bit 2s complement signed integers.
  • Page 55: Table 5.1. Adc0 Electrical Characteristics

    C8051F330/1/2/3/4/5 Table 5.1. ADC0 Electrical Characteristics – = 3.0 V, VREF = 2.40 V (REFSL=0), 40 to +85 °C unless otherwise specified. Parameter Conditions Units DC Accuracy Resolution bits Integral Nonlinearity — ±0.5 ±1 Differential Nonlinearity Guaranteed Monotonic — ±0.5 ±1...
  • Page 56 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 57: Bit Current Mode Dac (Ida0, C8051F330 Only)

    6. 10-Bit Current Mode DAC (IDA0, C8051F330 only) The C8051F330 device includes a 10-bit current-mode Digital-to-Analog Converter (IDAC). The maximum current output of the IDAC can be adjusted for three different current settings; 0.5 mA, 1 mA, and 2 mA.
  • Page 58: Update Output Based On Timer Overflow

    C8051F330/1/2/3/4/5 6.1.2. Update Output Based on Timer Overflow Similar to the ADC operation, in which an ADC conversion can be initiated by a timer overflow inde- pendently of the processor, the IDAC outputs can use a Timer overflow to schedule an output update event.
  • Page 59 C8051F330/1/2/3/4/5 SFR Definition 6.1. IDA0CN: IDA0 Control Reset Value IDA0EN IDA0CM IDA0OMD 01110010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB9 Bit 7: IDA0EN: IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. Bits 6–4: IDA0CM[2:0]: IDA0 Update Source Select bits.
  • Page 60: Table 6.1. Idac Electrical Characteristics

    C8051F330/1/2/3/4/5 SFR Definition 6.3. IDA0L: IDA0 Data Word LSB Reset Value — — — — — — 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x96 Bits 7–6: IDA0 Data Word Low-Order Bits. Lower 2 bits of the 10-bit Data Word.
  • Page 61: Voltage Reference (C8051F330/2/4 Only)

    C8051F330/1/2/3/4/5 Voltage Reference (C8051F330/2/4 only) The Voltage reference MUX on the C8051F330/2/4 devices is configurable to use an externally connected voltage reference, the internal reference voltage generator, or the V power supply voltage (see Figure 7.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For an external source or the internal reference, REFSL should be set to ‘0’.
  • Page 62 C8051F330/1/2/3/4/5 SFR Definition 7.1. REF0CN: Reference Control Reset Value REFSL TEMPE BIASE REFBE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD1 Bits7–4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference.
  • Page 63: Table 7.1. Voltage Reference Electrical Characteristics

    C8051F330/1/2/3/4/5 Table 7.1. Voltage Reference Electrical Characteristics = 3.0 V; –40 to +85 °C unless otherwise specified. Parameter Conditions Units Internal Reference (REFBE = 1) Output Voltage 25 °C ambient 2.38 2.44 2.50 VREF Short-Circuit Current — — VREF Temperature —...
  • Page 64 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 65: Comparator0

    C8051F330/1/2/3/4/5 Comparator0 C8051F330/1/2/3/4/5 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 8.1. The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn- chronous “raw”...
  • Page 66: Figure 8.2. Comparator Hysteresis Plot

    C8051F330/1/2/3/4/5 The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis- abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and its supply current falls to less than 100 nA.
  • Page 67 C8051F330/1/2/3/4/5 logic 1 upon a Comparator falling-edge occurrence, and the CP0RIF flag is set to logic 1 upon the Com- parator rising-edge occurrence. Once set, these bits remain set until cleared by software. The Comparator rising-edge interrupt mask is enabled by setting CP0RIE to a logic 1. The Comparator0 falling-edge inter- rupt mask is enabled by setting CP0FIE to a logic 1.
  • Page 68 C8051F330/1/2/3/4/5 SFR Definition 8.2. CPT0MX: Comparator0 MUX Selection Reset Value CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 CMX0P0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9F Bits7–4: CMX0N3–CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative input.
  • Page 69 C8051F330/1/2/3/4/5 SFR Definition 8.3. CPT0MD: Comparator0 Mode Selection Reset Value CP0RIE CP0FIE CP0MD1 CP0MD0 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x9D Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable.
  • Page 70: Table 8.1. Comparator Electrical Characteristics

    C8051F330/1/2/3/4/5 Table 8.1. Comparator Electrical Characteristics = 3.0 V, –40 to +85 °C unless otherwise noted. Parameter Conditions Units CP0+ – CP0– = 100 mV — — Response Time: Mode 0, Vcm = 1.5 V CP0+ – CP0– = –100 mV —...
  • Page 71: Microcontroller

    C8051F330/1/2/3/4/5 CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are...
  • Page 72: Instruction Set

    9.1.2. MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F330/1/2/3/4/5 does not support off-chip data or program memory). In the CIP-51, the MOVX instruction can be used to access on-chip XRAM or on-chip program memory space implemented as re-programmable Flash mem- ory.
  • Page 73: Table 9.1. Cip-51 Instruction Set Summary

    C8051F330/1/2/3/4/5 program memory space for non-volatile data storage. Refer to Section “11. Flash Memory” on page 103 for further details. Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description Bytes Clock Cycles Arithmetic Operations ADD A, Rn Add register to A...
  • Page 74 C8051F330/1/2/3/4/5 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive-OR A to direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A...
  • Page 75 C8051F330/1/2/3/4/5 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description Bytes Clock Cycles CPL C Complement Carry CPL bit Complement direct bit ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry...
  • Page 76: Memory Organization

    C8051F330/1/2/3/4/5 Notes on Registers, Operands and Addressing Modes: Rn - Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps.
  • Page 77: Program Memory

    Figure 9.2. Memory Map 9.2.1. Program Memory The CIP-51 core has a 64 kB program memory space. The C8051F330/1 implements 8 kB of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous block from addresses 0x0000 to 0x1DFF. Addresses above 0x1DFF are reserved on the 8 kB devices. The C8051F332/3 and C8051F334/5 implement, in contiguous blocks, 2 and 4 kB, from addresses 0x0000 to 0x07FF or 0x0000 to 0x0FFF, respectively.
  • Page 78: Data Memory

    C8051F330/1/2/3/4/5 9.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Loca- tions 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers.
  • Page 79: Special Function Registers

    C8051F330/1/2/3/4/5 9.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU.
  • Page 80: Table 9.3. Special Function Registers

    C8051F330/1/2/3/4/5 Table 9.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3...
  • Page 81 C8051F330/1/2/3/4/5 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page OSCXCN 0xB1 External Oscillator Control 0x80 Port 0 Latch P0MDIN 0xF1 Port 0 Input Mode Configuration P0MDOUT...
  • Page 82 C8051F330/1/2/3/4/5 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description Page 0x81 Stack Pointer SPI0CFG 0xA1 SPI Configuration SPI0CKR 0xA2 SPI Clock Rate Control SPI0CN 0xF8 SPI Control...
  • Page 83: Register Descriptions

    C8051F330/1/2/3/4/5 9.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default state.
  • Page 84 C8051F330/1/2/3/4/5 SFR Definition 9.4. PSW: Program Status Word Reset Value PARITY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD0 (bit addressable) Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction).
  • Page 85: Interrupt Handler

    C8051F330/1/2/3/4/5 SFR Definition 9.5. ACC: Accumulator Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE0 (bit addressable) Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations.
  • Page 86: Mcu Interrupt Sources And Vectors

    C8051F330/1/2/3/4/5 EA = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: CLR EA ; clear EA bit. CLR EA ; this is a dummy instruction with two-byte opcode. If an interrupt is posted during the execution phase of a "CLR EA" opcode (or any instruction which clears the EA bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken.
  • Page 87: External Interrupts

    C8051F330/1/2/3/4/5 9.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low;...
  • Page 88: Table 9.4. Interrupt Summary

    C8051F330/1/2/3/4/5 Table 9.4. Interrupt Summary Interrupt Priority Enable Priority Interrupt Source Pending Flag Vector Order Flag Control Always Always Reset 0x0000 None N/A N/A Enabled Highest External Interrupt 0 0x0003 IE0 (TCON.1) EX0 (IE.0) PX0 (IP.0) (/INT0) Timer 0 Overflow 0x000B TF0 (TCON.5)
  • Page 89: Interrupt Register Descriptions

    C8051F330/1/2/3/4/5 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
  • Page 90 C8051F330/1/2/3/4/5 SFR Definition 9.8. IP: Interrupt Priority Reset Value PSPI0 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB8 (bit addressable) Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control.
  • Page 91 C8051F330/1/2/3/4/5 SFR Definition 9.9. EIE1: Extended Interrupt Enable 1 Reset Value Reserved ECP0 EPCA0 EADC0 EWADC0 Reserved ESMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE6 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt.
  • Page 92 C8051F330/1/2/3/4/5 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 Reset Value Reserved PCP0 PPCA0 PADC0 PWADC0 Reserved PSMB0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF6 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt.
  • Page 93 C8051F330/1/2/3/4/5 SFR Definition 9.11. IT01CF: INT0/INT1 Configuration Reset Value IN1PL IN1SL2 IN1SL1 IN1SL0 IN0PL IN0SL2 IN0SL1 IN0SL0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE4 *Note: Refer to SFR Definition 18.1 for INT0/1 edge- or level-sensitive interrupt selection.
  • Page 94: Power Management Modes

    C8051F330/1/2/3/4/5 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states;...
  • Page 95: Stop Mode

    C8051F330/1/2/3/4/5 9.4.2. Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripher- als are stopped;...
  • Page 96 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 97: Reset Sources

    C8051F330/1/2/3/4/5 10. Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their defined reset values •...
  • Page 98: Power-On Reset

    C8051F330/1/2/3/4/5 10.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until V settles above . A delay occurs before the device is released from reset; the delay decreases as the V...
  • Page 99: External Reset

    C8051F330/1/2/3/4/5 Important Note: The V monitor must be enabled before it is selected as a reset source. Selecting the monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce- dure for configuring the V monitor as a reset source is shown below: Step 1.
  • Page 100: Comparator0 Reset

    C8051F330/1/2/3/4/5 10.5. Comparator0 Reset Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Com- parator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset.
  • Page 101 C8051F330/1/2/3/4/5 SFR Definition 10.2. RSTSRC: Reset Source Reset Value FERROR C0RSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xEF SFR Address: Note: Do not use read-modify-write operations (ORL, ANL) on this register. Bit7: UNUSED.
  • Page 102: Table 10.1. Reset Electrical Characteristics

    C8051F330/1/2/3/4/5 Table 10.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter Conditions Units = 8.5 mA, RST Output Low Voltage — — = 2.7 V to 3.6 V 0.7 x V RST Input High Voltage — —...
  • Page 103: Flash Memory

    C8051F330/1/2/3/4/5 11. Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the MOVX instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1.
  • Page 104: Flash Write Procedure

    C8051F330/1/2/3/4/5 11.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in Section 11.1.2 Step 3. Set the PSWE bit (register PSCTL).
  • Page 105: Security Options

    C8051F330/1/2/3/4/5 11.3. Security Options The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft- ware as well as to prevent the viewing of proprietary program code and constants. The Program Store Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register PSCTL) bits protect the Flash memory from accidental modification by software.
  • Page 106: Table 11.2. Flash Security Summary

    C8051F330/1/2/3/4/5 The level of Flash security depends on the Flash access method. The three Flash access methods that can be restricted are reads, writes, and erases from the C2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. Table 11.2 summarizes the Flash security features of the 'F330/1/2/3/4/5 devices.
  • Page 107: Flash Write And Erase Guidelines

    Code examples showing this can be found in “AN201: Writing to Flash from Firmware", avail- able from the Silicon Laboratories web site. 4. As an added precaution, explicitly enable the V monitor and enable the V monitor as a reset source inside the functions that write and erase Flash memory.
  • Page 108: System Clock

    Flash operation has completed. Additional Flash recommendations and example code can be found in AN201, "Writing to Flash from Firm- ware", available from the Silicon Laboratories web site. SFR Definition 11.1. PSCTL: Program Store R/W Control Reset Value —...
  • Page 109 C8051F330/1/2/3/4/5 SFR Definition 11.2. FLKEY: Flash Lock and Key Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xB7 SFR Address: Bits7–0: FLKEY: Flash Lock and Key Register Write: This register provides a lock and key function for Flash erasures and writes. Flash writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register.
  • Page 110 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 111: External Ram

    C8051F330/1/2/3/4/5 12. External RAM The C8051F330/1/2/3/4/5 devices include 512 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. If the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Interface Control Register (EMI0CN as shown in SFR Definition 12.1).
  • Page 112 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 113: Oscillators

    The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 13.1. On C8051F330/1/2/3/4/5 devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency. Electrical specifications for the precision internal oscillator are given in Table 13.1 on page 122. Note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defined by the IFCN bits in register OSCICN.
  • Page 114 This register determines the internal oscillator period. When set to 0000000b, the H-F oscil- lator operates at its fastest setting. When set to 1111111b, the H-F oscillator operates at its slowest setting. On C8051F330/1/2/3/4/5 devices, the reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz.
  • Page 115: Programmable Internal Low-Frequency (L-F) Oscillator

    C8051F330/1/2/3/4/5 13.2. Programmable Internal Low-Frequency (L-F) Oscillator All C8051F330/1/2/3/4/5 devices include a programmable low-frequency internal oscillator, which is cali- brated to a nominal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock by 1, 2, 4, or 8, using the OSCLD bits in the OSCLCN register (see SFR Defi- nition 13.3).
  • Page 116: External Oscillator Drive Circuit

    C8051F330/1/2/3/4/5 13.3. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor, or RC network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 13.1. A 10 MΩ...
  • Page 117 C8051F330/1/2/3/4/5 SFR Definition 13.4. OSCXCN: External Oscillator Control Reset Value XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 XFCN2 XFCN1 XFCN0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB1 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable.
  • Page 118: External Crystal Example

    C8051F330/1/2/3/4/5 13.3.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 1. The External Oscillator Frequency Control value (XFCN) should be chosen from the Crystal column of the table in SFR Definition 13.4 (OSCXCN register).
  • Page 119: Figure 13.2. External 32.768 Khz Quartz Crystal Oscillator Connection Diagram

    C8051F330/1/2/3/4/5 The capacitors shown in the external crystal configuration provide the load capacitance required by the crystal for correct oscillation. These capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the XTAL1 and XTAL2 pins.
  • Page 120: External Rc Example

    C8051F330/1/2/3/4/5 13.3.2. External RC Example If an RC network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 13.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout.
  • Page 121: System Clock Selection

    C8051F330/1/2/3/4/5 13.4. System Clock Selection The internal oscillator requires little start-up time and may be selected as the system clock immediately fol- lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ- ically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to '1' by hardware when the external oscillator is settled.
  • Page 122: Table 13.1. Internal Oscillator Electrical Characteristics

    C8051F330/1/2/3/4/5 Table 13.1. Internal Oscillator Electrical Characteristics = 2.7 to 3.6 V; T = –40 to +85 °C unless otherwise specified Parameter Conditions Units Internal High-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency IFCN = 11b 24.5 25 °C, V = 3.0 V, Oscillator Supply Current —...
  • Page 123: Port Input/Output

    C8051F330/1/2/3/4/5 14. Port Input/Output Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide Ports and one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input;...
  • Page 124: Figure 14.2. Port I/O Cell Block Diagram

    C8051F330/1/2/3/4/5 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE (WEAK) PORT PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 14.2. Port I/O Cell Block Diagram Rev. 1.7...
  • Page 125: Priority Crossbar Decoder

    C8051F330/1/2/3/4/5 14.1. Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 14.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips that pin when assigning the next selected resource.
  • Page 126: Figure 14.4. Crossbar Priority Decoder With Crystal Pins Skipped

    C8051F330/1/2/3/4/5 SF Signals VREF IDA CNVSTR PIN I/O MISO MOSI *NSS is only pinned out in 4-wire SPI Mode NSS* CP0A SYSCLK CEX0 CEX1 CEX2 P0SKIP[0:7] P1SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the crossbar.
  • Page 127: Port I/O Initialization

    C8051F330/1/2/3/4/5 14.2. Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT).
  • Page 128 C8051F330/1/2/3/4/5 SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0 Reset Value CP0AE CP0E SYSCKE SMB0E SPI0E URT0E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE1 Bits7–6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin.
  • Page 129: General Purpose Port I/O

    C8051F330/1/2/3/4/5 SFR Definition 14.2. XBR1: Port I/O Crossbar Register 1 Reset Value WEAKPUD XBARE ECIE PCA0ME 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xE2 Bit7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input).
  • Page 130 C8051F330/1/2/3/4/5 SFR Definition 14.3. P0: Port0 Reset Value P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x80 (bit addressable) Bits7–0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers.
  • Page 131 C8051F330/1/2/3/4/5 SFR Definition 14.5. P0MDOUT: Port0 Output Mode Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA4 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0.
  • Page 132 C8051F330/1/2/3/4/5 SFR Definition 14.8. P1MDIN: Port1 Input Mode Reset Value 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF2 Bits7–0: Analog Input Configuration Bits for P1.7–P1.0 (respectively). Port pins configured as analog inputs have their weak pullup, digital driver, and digital receiver disabled.
  • Page 133 C8051F330/1/2/3/4/5 SFR Definition 14.11. P2: Port2 Reset Value P2.0 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA0 (bit addressable) Bits7–1: Unused. Read = 0000000b. Write = don’t care. Bit0: P2.0 Write - Output appears on I/O pins per Crossbar Registers.
  • Page 134: Table 14.1. Port I/O Dc Electrical Characteristics

    C8051F330/1/2/3/4/5 Table 14.1. Port I/O DC Electrical Characteristics = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified. Parameters Conditions Units = –3 mA, Port I/O push-pull – 0.7 — — — = –10 µA, Port I/O push-pull Output High Voltage –...
  • Page 135: Smbus

    C8051F330/1/2/3/4/5 15. SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data.
  • Page 136: Supporting Documents

    C8051F330/1/2/3/4/5 15.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor. 3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.
  • Page 137: Arbitration

    C8051F330/1/2/3/4/5 The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit.
  • Page 138: Clock Low Extension

    C8051F330/1/2/3/4/5 15.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency.
  • Page 139 C8051F330/1/2/3/4/5 SMBus configuration options include: • Timeout detection (SCL Low Timeout and/or Bus Free Timeout) • SDA setup and hold time extensions • Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in Section “15.4.1.
  • Page 140: Smbus Configuration Register

    C8051F330/1/2/3/4/5 15.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit.
  • Page 141: Figure 15.4. Typical Smbus Scl Generation

    C8051F330/1/2/3/4/5 Figure 15.4 shows the typical SCL generation described by Equation 15.2. Notice that T is typically HIGH twice as large as T . The actual SCL output may vary due to other devices on the bus (SCL may be extended low by slower slave devices, or driven low by contending master devices).
  • Page 142 C8051F330/1/2/3/4/5 SFR Definition 15.1. SMB0CF: SMBus Clock/Configuration Reset Value ENSMB BUSY EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCS0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0xC1 SFR Address: Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins.
  • Page 143: Smb0Cn Control Register

    C8051F330/1/2/3/4/5 15.4.2. SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 15.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines.
  • Page 144 C8051F330/1/2/3/4/5 SFR Definition 15.2. SMB0CN: SMBus Control Reset Value MASTER TXMODE ACKRQ ARBLOST 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable 0xC0 SFR Address: Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master.
  • Page 145: Table 15.3. Sources For Hardware Changes To Smb0Cn

    C8051F330/1/2/3/4/5 Table 15.3. Sources for Hardware Changes to SMB0CN Set by Hardware When: Cleared by Hardware When: • A STOP is generated. MASTER • A START is generated. • Arbitration is lost. • A START is detected. • START is generated.
  • Page 146: Data Register

    C8051F330/1/2/3/4/5 15.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register.
  • Page 147: Figure 15.5. Typical Master Transmitter Sequence

    C8051F330/1/2/3/4/5 Data Byte Data Byte Interrupt Interrupt Interrupt Interrupt S = START Received by SMBus P = STOP Interface A = ACK Transmitted by W = WRITE SLA = Slave Address SMBus Interface Figure 15.5. Typical Master Transmitter Sequence Rev. 1.7...
  • Page 148: Master Receiver Mode

    C8051F330/1/2/3/4/5 15.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc- tion bit.
  • Page 149: Slave Receiver Mode

    C8051F330/1/2/3/4/5 15.5.3. Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit (WRITE in this case) is received.
  • Page 150: Slave Transmitter Mode

    C8051F330/1/2/3/4/5 15.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received.
  • Page 151: Table 15.4. Smbus Status Decoding

    C8051F330/1/2/3/4/5 Table 15.4. SMBus Status Decoding Values Values Read Written Current SMbus State Typical Response Options Load slave address + R/W 1110 X A master START was generated. into SMB0DAT. Set STA to restart transfer. A master data or address byte was transmitted;...
  • Page 152 C8051F330/1/2/3/4/5 Table 15.4. SMBus Status Decoding Values Values Read Written Current SMbus State Typical Response Options A slave byte was transmitted; No action required (expect- NACK received. ing STOP condition). A slave byte was transmitted; Load SMB0DAT with next 0100 ACK received.
  • Page 153: Uart0

    C8051F330/1/2/3/4/5 16. UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details Section “16.1. Enhanced Baud Rate Generation” on page 154 ).
  • Page 154: Enhanced Baud Rate Generation

    C8051F330/1/2/3/4/5 16.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 16.2), which is not user- accessible.
  • Page 155: Operational Modes

    C8051F330/1/2/3/4/5 16.2. Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. RS-232 RS-232 C8051Fxxx LEVEL XLTR C8051Fxxx Figure 16.3. UART Interconnect Diagram 16.2.1.
  • Page 156: 9-Bit Uart

    C8051F330/1/2/3/4/5 16.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software.
  • Page 157: Figure 16.6. Uart Multi-Processor Mode Interconnect Diagram

    C8051F330/1/2/3/4/5 Master Slave Slave Slave Device Device Device Device Figure 16.6. UART Multi-Processor Mode Interconnect Diagram Rev. 1.7...
  • Page 158 C8051F330/1/2/3/4/5 SFR Definition 16.1. SCON0: Serial Port 0 Control Reset Value S0MODE MCE0 REN0 TB80 RB80 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable 0x98 SFR Address: Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode.
  • Page 159 C8051F330/1/2/3/4/5 SFR Definition 16.2. SBUF0: Serial (UART0) Port Data Buffer Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x99 SFR Address: Bits7 – 0: SBUF0[7:0]: Serial Data Buffer Bits 7 – 0 (MSB – LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF0, it goes to the transmit shift register and is held for serial transmis- sion.
  • Page 160: Table 16.1. Timer Settings For Standard Baud Rates Using The Internal 24.5 Mhz Oscillator

    C8051F330/1/2/3/4/5 Table 16.1. Timer Settings for Standard Baud Rates Using the Internal 24.5 MHz Oscillator Frequency: 24.5 MHz Target Baud Rate Oscilla- Timer Clock SCA1–SCA0 Timer 1 Baud Rate % Error tor Divide Source (pre-scale Reload (bps) Factor Value (hex)
  • Page 161: Table 16.3. Timer Settings For Standard Baud Rates Using An External 22.1184 Mhz Oscillator

    C8051F330/1/2/3/4/5 Table 16.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Oscillator Frequency: 22.1184 MHz Target Baud Rate Oscilla- Timer Clock SCA1–SCA0 Timer 1 Baud Rate % Error tor Divide Source (pre-scale Reload (bps) Factor Value (hex)
  • Page 162: Table 16.5. Timer Settings For Standard Baud Rates Using An External 11.0592 Mhz Oscillator

    C8051F330/1/2/3/4/5 Table 16.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator Frequency: 11.0592 MHz Target Baud Rate Oscilla- Timer Clock SCA1–SCA0 Timer 1 Baud Rate % Error tor Divide Source (pre-scale Reload (bps) Factor Value (hex)
  • Page 163: Enhanced Serial Peripheral Interface (Spi0)

    C8051F330/1/2/3/4/5 17. Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single SPI bus.
  • Page 164: Signal Descriptions

    C8051F330/1/2/3/4/5 17.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 17.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to serially transfer data from the master to the slave.
  • Page 165: Spi0 Master Mode Operation

    C8051F330/1/2/3/4/5 17.2. SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data register (SPI0DAT) when in master mode writes to the transmit buffer.
  • Page 166: Figure 17.2. Multiple-Master Mode Connection Diagram

    C8051F330/1/2/3/4/5 GPIO MISO MISO Master Master MOSI MOSI Device 1 Device 2 GPIO Figure 17.2. Multiple-Master Mode Connection Diagram Master Slave Device Device MISO MISO MOSI MOSI Figure 17.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram Master...
  • Page 167: Spi0 Slave Mode Operation

    C8051F330/1/2/3/4/5 17.3. SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig- nal.
  • Page 168: Serial Clock Timing

    C8051F330/1/2/3/4/5 17.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock.
  • Page 169: Spi Special Function Registers

    C8051F330/1/2/3/4/5 (CKPOL=0, CKPHA=0) (CKPOL=1, CKPHA=0) MOSI Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NSS (4-Wire Mode) Figure 17.6. Slave Mode Data/Clock Timing (CKPHA = 0)
  • Page 170 C8051F330/1/2/3/4/5 SFR Definition 17.1. SPI0CFG: SPI0 Configuration Reset Value SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA1 Bit 7: SPIBSY: SPI Busy (read only). This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode).
  • Page 171 C8051F330/1/2/3/4/5 SFR Definition 17.2. SPI0CN: SPI0 Control Reset Value SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 TXBMT SPIEN 00000110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xF8 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine.
  • Page 172 C8051F330/1/2/3/4/5 SFR Definition 17.3. SPI0CKR: SPI0 Clock Rate Reset Value SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA2 Bits 7 – 0: SCR7 – SCR0: SPI0 Clock Rate.
  • Page 173: Figure 17.8. Spi Master Timing (Ckpha = 0)

    C8051F330/1/2/3/4/5 SCK* MCKH MCKL MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.8. SPI Master Timing (CKPHA = 0) SCK* MCKH MCKL MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
  • Page 174: Figure 17.10. Spi Slave Timing (Ckpha = 0)

    C8051F330/1/2/3/4/5 SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 17.10. SPI Slave Timing (CKPHA = 0) SCK* MOSI MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
  • Page 175: Table 17.1. Spi Slave Timing Parameters

    C8051F330/1/2/3/4/5 Table 17.1. SPI Slave Timing Parameters Parameter Description Units Master Mode Timing (See Figure 17.8 and Figure 17.9) SCK High Time 1 x T — MCKH SYSCLK SCK Low Time 1 x T — MCKL SYSCLK MISO Valid to SCK Shift Edge...
  • Page 176 C8051F330/1/2/3/4/5 Rev. 1.7...
  • Page 177: Timers

    C8051F330/1/2/3/4/5 18. Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests.
  • Page 178: Mode 1: 16-Bit Counter/Timer

    C8051F330/1/2/3/4/5 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section “14.1. Priority Crossbar Decoder” on page 125 for information on selecting and configuring external I/O pins).
  • Page 179: Mode 2: 8-Bit Counter/Timer With Auto-Reload

    C8051F330/1/2/3/4/5 18.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0.
  • Page 180: Mode 3: Two 8-Bit Counter/Timers (Timer 0 Only)

    C8051F330/1/2/3/4/5 18.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0.
  • Page 181 C8051F330/1/2/3/4/5 SFR Definition 18.1. TCON: Timer Control Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x88 (bit addressable) Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared when the CPU vectors to the Timer 1 interrupt service routine.
  • Page 182 C8051F330/1/2/3/4/5 SFR Definition 18.2. TMOD: Timer Mode Reset Value GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M1 T0M0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x89 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
  • Page 183 C8051F330/1/2/3/4/5 SFR Definition 18.3. CKCON: Clock Control Reset Value T3MH T3ML T2MH T2ML SCA1 SCA0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8E Bit7: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8- bit timer mode.
  • Page 184 C8051F330/1/2/3/4/5 SFR Definition 18.4. TL0: Timer 0 Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x8A Bits 7 – 0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0.
  • Page 185: Timer 2

    C8051F330/1/2/3/4/5 18.2. Timer 2 Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the Timer 2 operation mode.
  • Page 186: 8-Bit Timers With Auto-Reload

    C8051F330/1/2/3/4/5 18.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH holds the reload value for TMR2H.
  • Page 187 C8051F330/1/2/3/4/5 SFR Definition 18.8. TMR2CN: Timer 2 Control Reset Value TF2H TF2L TF2LEN TF2CEN T2SPLIT — T2XCLK 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xC8 (bit addressable) Bit7: TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 2 overflows from 0xFFFF to 0x0000.
  • Page 188 C8051F330/1/2/3/4/5 SFR Definition 18.9. TMR2RLL: Timer 2 Reload Register Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xCA Bits 7 – 0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2.
  • Page 189: Timer 3

    C8051F330/1/2/3/4/5 18.3. Timer 3 Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the Timer 3 operation mode.
  • Page 190: 8-Bit Timers With Auto-Reload

    C8051F330/1/2/3/4/5 18.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 18.7. TMR3RLL holds the reload value for TMR3L; TMR3RLH holds the reload value for TMR3H.
  • Page 191 C8051F330/1/2/3/4/5 SFR Definition 18.13. TMR3CN: Timer 3 Control Reset Value TF3H TF3L TF3LEN TF3CEN T3SPLIT — T3XCLK 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x91 Bit7: TF3H: Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00. In 16 bit mode, this will occur when Timer 3 overflows from 0xFFFF to 0x0000.
  • Page 192 C8051F330/1/2/3/4/5 SFR Definition 18.14. TMR3RLL: Timer 3 Reload Register Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0x92 Bits 7 – 0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3.
  • Page 193: Programmable Counter Array

    C8051F330/1/2/3/4/5 19. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line (CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “14.1.
  • Page 194: Pca Counter/Timer

    C8051F330/1/2/3/4/5 19.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
  • Page 195: Capture/Compare Modules

    C8051F330/1/2/3/4/5 19.2. Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP- 51 system controller.
  • Page 196: Edge-Triggered Capture Mode

    C8051F330/1/2/3/4/5 19.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge).
  • Page 197: Software Timer (Compare) Mode

    C8051F330/1/2/3/4/5 19.2.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software.
  • Page 198: High-Speed Output Mode

    C8051F330/1/2/3/4/5 19.2.3. High-Speed Output Mode In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High- Speed Output mode.
  • Page 199: Frequency Output Mode

    C8051F330/1/2/3/4/5 19.2.4. Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of the square wave is then defined by Equation 19.3.
  • Page 200: 8-Bit Pulse Width Modulator Mode

    C8051F330/1/2/3/4/5 19.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
  • Page 201: 16-Bit Pulse Width Modulator Mode

    C8051F330/1/2/3/4/5 19.2.6. 16-Bit Pulse Width Modulator Mode A PCA module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare mod- ule defines the number of PCA clocks for the low time of the PWM signal. When the PCA counter matches the module contents, the output on CEXn is asserted high;...
  • Page 202: Watchdog Timer Operation

    C8051F330/1/2/3/4/5 19.3.1. Watchdog Timer Operation While the WDT is enabled: • PCA counter is forced on. • Writes to PCA0L and PCA0H are not allowed. • PCA clock source bits (CPS2 – CPS0) are frozen. • PCA Idle control bit (CIDL) is frozen.
  • Page 203: Watchdog Timer Usage

    C8051F330/1/2/3/4/5 Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed.
  • Page 204: Register Descriptions For Pca

    C8051F330/1/2/3/4/5 Table 19.4. Watchdog Timer Timeout Intervals System Clock (Hz) PCA0CPL2 Timeout Interval (ms) 24,500,000 32.1 24,500,000 16.2 24,500,000 18,432,000 42.7 18,432,000 21.5 18,432,000 11,059,200 71.1 11,059,200 35.8 11,059,200 3,062,500 129.5 3,062,500 33.1 3,062,500 32,000 24576 32,000 12384 32,000 3168 Notes: 1.
  • Page 205 C8051F330/1/2/3/4/5 SFR Definition 19.1. PCA0CN: PCA Control Reset Value CCF2 CCF1 CCF0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Addressable SFR Address: 0xD8 Bit7: CF: PCA Counter/Timer Overflow Flag. Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine.
  • Page 206 C8051F330/1/2/3/4/5 SFR Definition 19.2. PCA0MD: PCA Mode Reset Value CIDL WDTE WDLCK — CPS2 CPS1 CPS0 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD9 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode.
  • Page 207 C8051F330/1/2/3/4/5 SFR Definition 19.3. PCA0CPMn: PCA Capture/Compare Mode Reset Value PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: PCA0CPM0: 0xDA, PCA0CPM1: 0xDB, PCA0CPM2: 0xDC Bit7: PWM16n: 16-bit Pulse Width Modulation Enable.
  • Page 208 C8051F330/1/2/3/4/5 SFR Definition 19.4. PCA0L: PCA Counter/Timer Low Byte Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xF9 Bits 7 – 0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer.
  • Page 209: C2 Interface

    C8051F330/1/2/3/4/5 20. C2 Interface C8051F330/1/2/3/4/5 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow Flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data signal (C2D) to transfer information between the device and a host system.
  • Page 210 C8051F330/1/2/3/4/5 C2 Register Definition 20.3. REVID: C2 Revision ID Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 This read-only register returns the 8-bit revision ID: 0x00 (Revision A). C2 Register Definition 20.4. FPCTL: C2 Flash Programming Control...
  • Page 211: C2 Pin Sharing

    C8051F330/1/2/3/4/5 20.2. C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and Flash programming may be performed. This is possible because C2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. In this halted state, the C2 interface can safely ‘borrow’...
  • Page 212 • Removed references to C8051F330D throughout the data sheet because the 'F330D device is func- tionally identical to the C8051F330 device (these two part numbers differ by package type only). • Updated titles of Chapters 5, 6, and 7 to show supported devices.
  • Page 213 C8051F330/1/2/3/4/5 OTES Rev. 1.7...
  • Page 214 The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death.

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