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Silicon Laboratories EFR32 G23 Series Reference Manual

Wireless soc

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EFR32xG23 Wireless SoC

Reference Manual

The EFR32xG23 Wireless SoCs include the EFR32FG23 and EFR32ZG23 Wireless

SoC device families. The EFR32xG23 SoC is an ideal solution for sub-GHz "Internet of

Things" for smart home, security, lighting, building automation, and metering. The high-

performance sub-GHz radio provides long range and is not susceptible to 2.4 GHz inter-

ference from technologies like Wi-Fi.

The single die, multi-core solution, provides industry leading security, low power con-

sumption with fast wakeup times, and an integrated power amplifier, to enable the next

level of secure connectivity for IoT devices.

Core / Memory

ARM Cortex

TM

M33 processor

with DSP extensions,

FPU and TrustZone

ETM

Debug Interface

Radio Subsystem

RX/TX Frontend with

Integrated +14 or 20 dBm PA

Frequency Synthesizer

Lowest power mode with peripheral operational:

EM0—Active

silabs.com | Building a more connected world.

Flash Program Memory

LDMA

RAM Memory

Controller

Peripheral Reflex System

Interfaces

ARM Cortex

TM

DEMOD

M0+ Radio

Controller

IFADC

BUFC RAM

AGC

FRC

MOD

CRC

EM1—Sleep

Copyright © 2022 by Silicon Laboratories

Clock Management

HF Crystal

HF

Oscillator

RC Oscillator

LF

Fast Startup

RC Oscillator

RC Oscillator

LF Crystal

Ultra LF RC

Oscillator

Oscillator

32-bit bus

Serial

I/O Ports

LCD

USART

Keypad Scanner

External

EUSART

Interrupts

General

Purpose I/O

EUSART

Pin Reset

I

2

C

Pin Wakeup

EM2—Deep Sleep

KEY FEATURES

• 32-bit ARM® Cortex M33 core with 78

MHz maximum operating frequency

• Up to 512 kB of flash and 64 kB of RAM

• Energy-efficient radio core with low active

and sleep currents

• Integrated PA with up to 20 dBm transmit

power

• Robust peripheral set and up to 31 GPIO

Energy Management

Crypto Acceleration

Number Generator

Voltage

DC-DC

Regulator

Converter

Countermeasures

Secure Debug

Authentication

Power-On

Brown-Out

Reset

Detector

Secure Engine

Timers and Triggers

Timer/Counter

Protocol Timer

Low Energy Timer

Watchdog Timer

System Real Time

Back-Up Real

Counter

Time Counter

LESENSE

Pulse Counter

EM3—Stop

Security

True Random

DPA

Analog I/F

IADC

ACMP

VDAC

Temperature

Sensor

EM4—Shutoff

Rev. 1.0

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Summary of Contents for Silicon Laboratories EFR32 G23 Series

Page 1 Time Counter Pin Reset Frequency Synthesizer Temperature LESENSE Pulse Counter Sensor Pin Wakeup Lowest power mode with peripheral operational: EM0—Active EM1—Sleep EM2—Deep Sleep EM3—Stop EM4—Shutoff silabs.com | Building a more connected world. Copyright © 2022 by Silicon Laboratories Rev. 1.0...
Page 2: Table Of Contents
Table of Contents 1. About This Document ......29 1.1 Introduction .......29 1.2 Conventions .
Page 3 6.3 Functional Description ......59 6.3.1 Ram Configuration ......59 6.3.2 Instruction Cache.
Page 4 6.8.16 MSC_PAGELOCK0 - Main Space Page 0-31 Lock Word ... . . 144 6.8.17 MSC_PAGELOCK1 - Main Space Page 32-63 Lock Word ... . 1 44 7.
Page 5 8.5.22 CMU_WDOG1CLKCTRL - Watchdog1 Clock Control ....185 8.5.23 CMU_EUSART0CLKCTRL - EUSART0 Clock Control ....186 8.5.24 CMU_SYSRTC0CLKCTRL - System RTC0 Clock Control .
Page 6 9.8 ULFRCO - Ultra Low Frequency RC Oscillator ....251 9.8.1 Introduction ......251 9.8.2 Features .
Page 7 11.2.2 Secure Boot with Root of Trust and Secure Loader (RTSL) ... . 282 11.2.3 Secure Debug ......282 11.2.4 Cryptographic Accelerator .
Page 8 12.5.18 EMU_DGIEN - Interrupt Enables Debug ....328 12.5.19 EMU_EFPIF - EFP Interrupt Register ....328 12.5.20 EMU_EFPIEN - EFP Interrupt Enable Register .
Page 9 13.5.21 PRS_CONSUMER_LDMAXBAR_DMAREQ0 - DMAREQ0 Consumer Register ..381 13.5.22 PRS_CONSUMER_LDMAXBAR_DMAREQ1 - DMAREQ1 Consumer Register ..382 13.5.23 PRS_CONSUMER_LESENSE_START - START Consumer Register ..382 13.5.24 PRS_CONSUMER_LETIMER0_CLEAR - CLEAR Consumer Register ..383 13.5.25 PRS_CONSUMER_LETIMER0_START - START Consumer Register .
Page 10 13.5.69 PRS_CONSUMER_TIMER2_CC2 - CC2 Consumer Register ... 405 13.5.70 PRS_CONSUMER_TIMER2_DTI - DTI Consumer Register ... 4 06 13.5.71 PRS_CONSUMER_TIMER2_DTIFS1 - DTI Consumer Register ..406 13.5.72 PRS_CONSUMER_TIMER2_DTIFS2 - DTI Consumer Register .
Page 11 14.5.8 GPCRC_INPUTDATAHWORD - Input 16-Bit Data Register ... . 432 14.5.9 GPCRC_INPUTDATABYTE - Input 8-Bit Data Register ... . . 4 32 14.5.10 GPCRC_DATA - CRC Data Register .
Page 12 16.5 BURTC Register Description ......454 16.5.1 BURTC_IPVERSION - IP Version ID....454 16.5.2 BURTC_EN - Module Enable Register .
Page 13 18.12.6 PWM Output ......4 79 18.13 LETIMER Register Map ......480 18.14 LETIMER Register Description .
Page 14 19.5.13 TIMER_CCx_CFG - CC Channel Configuration Register ... . 540 19.5.14 TIMER_CCx_CTRL - CC Channel Control Register ....542 19.5.15 TIMER_CCx_OC - OC Channel Value Register .
Page 15 20.5.15 USART_TXDATAX - TX Buffer Data Extended Register ... . . 607 20.5.16 USART_TXDATA - TX Buffer Data Register ....608 20.5.17 USART_TXDOUBLEX - TX Buffer Double Data Extended Register .
Page 16 21.5.20 EUSART_IF - Interrupt Flag Register ....682 21.5.21 EUSART_IEN - Interrupt Enable Register ....684 21.5.22 EUSART_SYNCBUSY - Synchronization Busy Register .
Page 17 23.3 Functional Description ......735 23.3.1 Register Access......736 23.3.2 Clocking .
Page 18 24.3.5 Configuration Lock ......796 24.3.6 EM2 Functionality ......796 24.3.7 EM4 Functionality .
Page 19 24.6.37 GPIO_LCDSEG - LCD Segment Enable ....892 24.6.38 GPIO_LCDCOM - LCD Common Enable ....892 24.6.39 GPIO_ACMP0_ROUTEEN - ACMP0 Pin Enable .
Page 20 24.6.85 GPIO_KEYSCAN_COLOUT5ROUTE - COLOUT5 Port/Pin Select ..918 24.6.86 GPIO_KEYSCAN_COLOUT6ROUTE - COLOUT6 Port/Pin Select ..919 24.6.87 GPIO_KEYSCAN_COLOUT7ROUTE - COLOUT7 Port/Pin Select ..919 24.6.88 GPIO_KEYSCAN_ROWSENSE0ROUTE - ROWSENSE0 Port/Pin Select .
Page 21 24.6.133 GPIO_PRS0_ROUTEEN - PRS0 Pin Enable ....945 24.6.134 GPIO_PRS0_ASYNCH0ROUTE - ASYNCH0 Port/Pin Select ..9 46 24.6.135 GPIO_PRS0_ASYNCH1ROUTE - ASYNCH1 Port/Pin Select .
Page 22: Timer Register Map
24.6.181 GPIO_TIMER4_CC1ROUTE - CC1 Port/Pin Select ....972 24.6.182 GPIO_TIMER4_CC2ROUTE - CC2 Port/Pin Select ....973 24.6.183 GPIO_TIMER4_CDTI0ROUTE - CDTI0 Port/Pin Select .
Page 23 25.7.7 LDMA_SYNCHWEN - DMA Sync HW Trigger Enable Register ...1014 25.7.8 LDMA_SYNCHWSEL - DMA Sync HW Trigger Selection Register ..1015 25.7.9 LDMA_SYNCSTATUS - DMA Sync Trigger Status Register .
Page 24 26.5.8 WDOG_LOCK - Lock Register ..... .1045 26.5.9 WDOG_SYNCBUSY - Synchronization Busy Register ....1045 27.
Page 25 28.2 Features ......1103 28.3 Functional Description ......1 104 28.3.1 Pulse Counter Modes .
Page 26 29.4.13 PRS ......1145 29.5 Programmer's Model ......1145 29.6 LESENSE Register Map .
Page 27 30.3.12 Output Mode ......1188 30.3.13 Internal Timers......1188 30.3.14 FIFO .
Page 28 31.5.5 ACMP_CTRL - Control Register ..... 1223 31.5.6 ACMP_INPUTCTRL - Input Control Register ....1 224 31.5.7 ACMP_STATUS - Status Register .
Page 29: About This Document
Reference Manual About This Document 1. About This Document 1.1 Introduction This document contains reference material for the EFR32xG23 devices. All modules and peripherals in the EFR32xG23 devices are described in general terms. Not all modules are present in all devices and the feature set for each device might vary. Such differences, including pinout, are covered in the device data sheets.
Page 30: Conventions
Reference Manual About This Document 1.2 Conventions Register Names Register names are given with a module name prefix followed by the short register name: TIMERn_CTRL - Control Register The "n" denotes the module number for modules which can exist in more than one instance. Some registers are grouped which leads to a group name following the module prefix: GPIO_Px_DOUT - Port Data Out Register The "x"...
Page 31: Related Documentation
Reference Manual About This Document The reset value denotes the value after reset. Registers denoted with X have unknown value out of reset and need to be initialized before use. Note that read-modify-write operations on these registers before they are initialized results in undefined register values. Pin Connections Pin connections are given with a module prefix followed by a short pin name: CMU_CLKOUT1 (Clock management unit, clock output pin number 1)
Page 32: System Overview
Reference Manual System Overview 2. System Overview Quick Facts What? The EFR32 Wireless Gecko is a highly integrated, configurable and low power wireless System-on- Chip (SoC) with a robust set of MCU and radio pe- ripherals. Why? The Radio enables support for protocols in sub-GHz frequency bands while the MCU system allows cus- tomized protocols and applications to run efficiently.
Page 33: Introduction
Reference Manual System Overview 2.1 Introduction The high level features of EFR32xG23 include: • High performance radio transceiver • Low power consumption in transmit, receive, and standby modes • Excellent receiver performance, including sensitivity, selectivity, and blocking • Excellent transmitter performance, including programmable output power, low phase noise, and power-amplifier (PA) ramping •...
Page 34: Block Diagrams
Reference Manual System Overview 2.2 Block Diagrams The block diagram for the EFR32xG23 System-On-Chip series is shown in (Figure 2.1 EFR32xG23 System-On-Chip Block Diagram on page 34). Core / Memory Clock Management Energy Management Security Crypto Acceleration HF Crystal True Random Oscillator RC Oscillator ARM Cortex...
Page 35: Mcu Features Overview
Reference Manual System Overview 2.3 MCU Features overview • ARM Cortex-M33 CPU platform • High Performance 32-bit processor @ up to 80 MHz • DSP instruction support and floating-point unit • Memory Protection Unit • Wake-up Interrupt Controller • Flexible Energy Management System •...
Page 36 Reference Manual System Overview • Timers/Counters • 1 × 32-bit and 4 × 16-bit Timer/Counters (TIMER) • 3 Compare/Capture/PWM channels • Dead-Time Insertion • 24-bit Low Energy Timer (LETIMER) • 32-bit Real-Time Counter (SYSRTC) • 32-bit Ultra Low Energy Backup Real Time Counter (BURTC) for periodic wake-up from any Energy Mode •...
Page 37: System Processor
Reference Manual System Processor 3. System Processor Quick Facts What? The EFR32xG23 features the industry leading Cor- tex-M33 CPU from ARM. Why? The ARM Cortex-M33 is designed for exceptionally short response time, high code density, and high 32- bit throughput while maintaining a strict cost and CM33 Core power consumption budget.
Page 38: Features
Reference Manual System Processor 3.2 Features • Harvard architecture • Separate data and program memory buses (No memory bottleneck as in a single bus system) • 3-stage pipeline • Thumb-2 instruction set • Enhanced levels of performance, energy efficiency, and code density •...
Page 39: Interrupt Operation
Reference Manual System Processor 3.3.1 Interrupt Operation Module Cortex-M NVIC IEN[n] Register SETENA[n]/CLRENA[n] Write Active interrupt Interrupt clear Interrupt request IF[n] condition clear SETPEND[n]/CLRPEND[n] Software generated interrupt Figure 3.1. Interrupt Operation The interrupt request (IRQ) lines are connected to the Cortex-M33. Each of these lines (shown in 3.3.3 Interrupt Request Lines (IRQ)) is connected to one or more interrupt flags in one or more modules.
Page 40: Interrupt Request Lines (Irq)
Reference Manual System Processor 3.3.3 Interrupt Request Lines (IRQ) This table shows all IRQ's for the system processor. M33 High Speed interrupts are indicated by an '*'. See the individual peripheral chapters for more information on interrupt function. IRQ # Name SMU_SECURE SMU_S_PRIVILEGED...
Page 41 Reference Manual System Processor IRQ # Name MODEM PROTIMER RAC_RSM RAC_SEQ HOSTMAILBOX SYNTH ACMP0 ACMP1 WDOG0 WDOG1 HFXO0 HFRCO0 HFRCOEM23 IADC DPLL0 EMUEFP DCDC VDAC PCNT0 KERNEL0 KERNEL1 M33CTI0 M33CTI1 FPUEXH SETAMPERHOST SEMBRX SEMBTX LESENSE SYSRTC_APP silabs.com | Building a more connected world. Rev.
Page 42 Reference Manual System Processor IRQ # Name SYSRTC_SEQ KEYSCAN RFECA0 RFECA1 silabs.com | Building a more connected world. Rev. 1.0 | 42...
Page 43: Memory And Bus System
Reference Manual Memory and Bus System 4. Memory and Bus System Quick Facts What? A low latency memory system including low energy Flash and RAM with data retention which makes the low energy modes attractive. Why? RAM retention reduces the need for storing data in Flash and enables frequent use of the ultra low en- ergy modes EM2 and EM3.
Page 44: Functional Description
Reference Manual Memory and Bus System 4.2 Functional Description The internal memory segments of the Cortex-M33 are mapped into the system memory map as shown by Figure 4.1 System Address Space with Core and Code Space Listing on page 0xfffffffe 0xe0100000 0xe00fffff M33 Peripherals...
Page 45: Bus Matrix
Reference Manual Memory and Bus System 4.2.1 Bus Matrix A multilayer AMBA AHB bus matrix connects the manager bus interfaces to the AHB subordinates. The bus matrix allows several AHB subordinates to be accessed simultaneously. An AMBA APB interface is used for the peripherals, which are accessed through an AHB- to-APB bridge connected to the AHB bus matrix.
Page 46: Flash
Reference Manual Memory and Bus System 4.2.1.2 Bus Faults System accesses from the core can receive a bus fault in the following condition(s): • The core attempts to access an address that is not assigned to any peripheral or other system device. These faults can be enabled or disabled by setting the ADDRFAULTEN bit in the SYSCFG_CTRL register.
Page 47: Gpio_Prs0_Asynch1Route - Asynch1 Port/Pin Select
Reference Manual Memory and Bus System 4.2.4.1 Peripheral Map This table shows the address range for each peripheral. In addition it shows the lowest energy mode in which the peripheral is pow- ered. Note that EM3 is defined as EM2 with all clocks disabled. Therefore all peripherals powered in EM2 are also powered in EM3 but may not function if they require a running clock.
Page 48 Reference Manual Memory and Bus System Address Range Module Name Power Domain 0x400B0000 - 0x400B3FFF KEYSCAN EM2 (PD0E) 0x400B4000 - 0x400B7FFF DMEM 0x400C0000 - 0x400C3FFF LCDRF 0x400C4000 - 0x400C7FFF PFMXPPRF 0x44000000 - 0x440007FF RADIOAES 0x44008000 - 0x4400BFFF 0x4400C000 - 0x4400FFFF 0x49000000 - 0x49003FFF LETIMER0 EM2 (PD0B)
Page 49 Reference Manual Memory and Bus System Address Range Module Name Power Domain 0x50048000 - 0x5004BFFF TIMER0_NS 0x5004C000 - 0x5004FFFF TIMER1_NS 0x50050000 - 0x50053FFF TIMER2_NS 0x50054000 - 0x50057FFF TIMER3_NS 0x50058000 - 0x5005BFFF TIMER4_NS 0x5005C000 - 0x5005FFFF USART0_NS 0x50064000 - 0x50067FFF BURTC_NS 0x50068000 - 0x5006BFFF I2C1_NS 0x50078000 - 0x5007BFFF...
Page 50 Reference Manual Memory and Bus System Address Range Module Name Power Domain 0x5B008000 - 0x5B00BFFF WDOG1_NS EM2, (PD0D) 0x5B010000 - 0x5B013FFF EUSART0_NS EM2, (PD0D) 0x5C000000 - 0x5C00007F SEMAILBOX_NS 0xA8004000 - 0xA8007FFF 0xA800C000 - 0xA800FFFF 0xA8010000 - 0xA8013FFF RFCRC 0xA8014000 - 0xA8017FFF MODEM 0xA8018000 - 0xA801BFFF SYNTH...
Page 51 Reference Manual Memory and Bus System 4.2.4.3 Peripheral Bit Set and Clear The EFR32xG23 supports bit set, bit clear, and bit toggle access to most peripheral registers. The bit set and bit clear functionality (also called Bit Access) enables modification of bit fields without the need to perform a read-modify-write. Also, the operation is contained within a single bus access.
Page 52 Reference Manual Memory and Bus System 4.2.4.4.4 LFSYNC Registers LFSYNC registers are used to communicate with running low frequency peripherals where PERCLK is expected to be much lower than the CPU clock and synchronization delays may be long. For example, a LETIMER running at 32 kHz when the core is at 78 MHz. In this case CPU stalls of several PERCLOCK cycles represent a significant blockage of the CPU and need to be avoided whenever possible.
Page 53: Radio Transceiver
Reference Manual Radio Transceiver 5. Radio Transceiver Quick Facts What? The Radio Transceiver provides access to transmit and receive data, radio settings and control inter- face. Why? The Radio Transceiver enables the user to commu- nicate using a wide range of data rates, modulation and frame formats.
Page 54: Introduction
Reference Manual Radio Transceiver 5.1 Introduction The Radio Transceiver of the EFR32 Series 2 enables the user to control a wide range of settings and options for tailoring radio opera- tion precisely to the users need. It provides access to the transmit and receive data buffers and supports both dynamic and static frame lengths, as well as automatic address filtering and CRC insertion/verification.
Page 55: Modulation Modes
Reference Manual Radio Transceiver 5.1.2 Modulation Modes EFR32xG23 supports a wide range of modulation modes in transmit and receive: • 2-FSK, 2-GFSK, 4-FSK, MSK, GMSK, O-QPSK with half-sine shaping, ASK / OOK, DBPSK TX • NRZ or Manchester support • UART mode over air for legacy protocols •...
Page 56: Frame Format Support
Reference Manual Radio Transceiver 5.1.7 Frame Format Support EFR32xG23 has an extensive support for frame handling in transmit and receive modes, which allows effective handling of even ad- vanced protocols. The frame format support is controlled by the Frame Controller (FRC). The support includes: •...
Page 57: Data Encryption And Authentication
Reference Manual Radio Transceiver 5.1.11 Data Encryption and Authentication EFR32xG23 has hardware support for AES encryption, decryption and authentication modes. These security operations can be per- formed on data in RAM or any data buffer, without further CPU intervention. The key size is 128 bits. AES modes of operations directly supported by the EFR32xG23 hardware are listed in Table 5.1 AES modes of operation with hard- ware support on page...
Page 58: Msc - Memory System Controller
Reference Manual MSC - Memory System Controller 6. MSC - Memory System Controller Quick Facts What? The user can perform flash memory read, read con- figuration, and write operations through the Memory System Controller (MSC). SRAM operation may be configured though System Configuration (SYSCFG). Why? 01000101011011100110010101110010 The MSC allows the application code and user data...
Page 59: Features
Reference Manual MSC - Memory System Controller 6.2 Features • AHB read interface • Scalable access performance to optimize the Cortex-M33 code interface • Advanced energy optimization functionality • Conditional branch target prefetch suppression • Cortex-M33 disfolding of if-then (IT) blocks •...
Page 60: Instruction Cache
Reference Manual MSC - Memory System Controller 6.3.2 Instruction Cache The instruction cache improves the speed and power consumption of the Cortex-M33 by providing fast, low-power access to recently executed instructions. For detailed information see 6.5 ICACHE - Instruction Cache 6.3.3 Device Information (DI) Page This read-only page holds calibration data from the production test, several unique device IDs, and other part specific information.
Page 61: Cortex-M33 If-Then Block Folding
Reference Manual MSC - Memory System Controller 6.3.10 Cortex-M33 If-Then Block Folding The Cortex-M33 offers a mechanism known as if-then block folding. This is a form of speculative prefetching where small if-then blocks are collapsed in the prefetch buffer if the condition evaluates to false. The instructions in the block then appear to execute in zero cy- cles.
Page 62: Erase And Write Operations
Reference Manual MSC - Memory System Controller 6.3.12 Erase and Write Operations The 20 MHz FSRCO is used for timing during flash write and erase operations. The default values in MSC_FLASHPROGRAMTIME and MSC_FLASHERASETIME contain the recommended programming configuration. To erase a page first set WREN in MSC_WRITECTRL and load any address in the page to be erased into the MSC_ADDRB register. Next check INVADDR, LOCKED, and WREADY in MSC_STATUS to ensure that the address is valid, not locked, and the MSC is ready to modify flash.
Page 63: Devinfo - Device Info Page
Reference Manual MSC - Memory System Controller 6.3.12.2 Flash Lock The ability to program or erase individual flash pages may be disabled using the MSC_PAGELOCKn registers. The bits in these regis- ters may only be set to 1 by software on the device and are cleared when the device is reset. This means that once locked, a page may not be unlocked until a reset occurs.
Page 64: Devinfo Register Map
Reference Manual MSC - Memory System Controller 6.4.1 DEVINFO Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DEVINFO_INFO DI Information 0x004 DEVINFO_PART Part Info 0x008 DEVINFO_MEMINFO Memory Info 0x00C DEVINFO_MSIZE Memory Size 0x010 DEVINFO_PKGINFO...
Page 65: Devinfo Register Description
Reference Manual MSC - Memory System Controller Offset Name Type Description 0x194 DEVINFO_IADC0HISPDOFF- IADC Offset Calibration SETCAL0 0x198 DEVINFO_IADC0HISPDOFF- IADC Offset Calibration SETCAL1 0x1FC DEVINFO_LEGACY Legacy Device Info 0x25C DEVINFO_RTHERM 6.4.2.37 DEVINFO_RTHERM - 6.4.2 DEVINFO Register Description 6.4.2.1 DEVINFO_INFO - DI Information Offset Bit Position 0x000...
Page 66 Reference Manual MSC - Memory System Controller 6.4.2.2 DEVINFO_PART - Part Info Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 67 Reference Manual MSC - Memory System Controller 6.4.2.3 DEVINFO_MEMINFO - Memory Info Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:16 DILEN Length of DI Page Length of DI area (number of 32-bit words included in CRC) 15:8 UDPAGESIZE User Data Page Size...
Page 68: Free Running Mode
Reference Manual MSC - Memory System Controller 6.4.2.5 DEVINFO_PKGINFO - Misc Device Info Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 69 Reference Manual MSC - Memory System Controller 6.4.2.6 DEVINFO_CUSTOMINFO - Custom Part Info Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 PARTNO Part Number Custom part identifier as unsigned integer (eg. 903). 65535 for standard product 15:0 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un-...
Page 70 Reference Manual MSC - Memory System Controller 6.4.2.8 DEVINFO_SWCAPA0 - Software Restriction Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 71 Reference Manual MSC - Memory System Controller Name Reset Access Description 15:14 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 13:12 BTSMART Bluetooth Smart Capability Bluetooth SMART stack capability level Value Mode...
Page 72 Reference Manual MSC - Memory System Controller 6.4.2.9 DEVINFO_SWCAPA1 - Software Restriction Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 73 Reference Manual MSC - Memory System Controller 6.4.2.10 DEVINFO_EXTINFO - External Component Info Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 74 Reference Manual MSC - Memory System Controller 6.4.2.11 DEVINFO_EUI48L - EUI 48 Low Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:24 OUI48L OUI48L Lower Octet of EUI48 Organizationally Unique Identifier 23:0 UNIQUEID Unique ID Unique identifier 6.4.2.12 DEVINFO_EUI48H - EUI 48 High Offset Bit Position...
Page 75 Reference Manual MSC - Memory System Controller 6.4.2.13 DEVINFO_EUI64L - EUI64 Low Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:0 UNIQUEL UNIQUEL Lower 32 bits of EUI64 Unique Identifier 6.4.2.14 DEVINFO_EUI64H - EUI64 High Offset Bit Position 0x04C Reset Access...
Page 76 Reference Manual MSC - Memory System Controller 6.4.2.15 DEVINFO_CALTEMP - Calibration Temperature Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 77 Reference Manual MSC - Memory System Controller 6.4.2.17 DEVINFO_HFRCODPLLCALn - HFRCODPLL Calibration Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:28 IREFTC Tempco Trim 27:26 CMPSEL Comparator Load Select 25:24 CLKDIV Locally Divide HFRCO Clock Output 23:21 CMPBIAS Comparator Bias Current 20:16...
Page 78 Reference Manual MSC - Memory System Controller 6.4.2.18 DEVINFO_HFRCOEM23CALn - HFRCOEM23 Calibration Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:28 IREFTC Tempco Trim 27:26 CMPSEL Comparator Load Select 25:24 CLKDIV Locally Divide HFRCO Clock Output 23:21 CMPBIAS Comparator Bias Current 20:16...
Page 79 Reference Manual MSC - Memory System Controller 6.4.2.19 DEVINFO_MODULENAME0 - Module Name Information Offset Bit Position 0x130 Reset Access Name Name Reset Access Description 31:24 MODCHAR4 0xFF Fourth character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR3 0xFF...
Page 80 Reference Manual MSC - Memory System Controller 6.4.2.21 DEVINFO_MODULENAME2 - Module Name Information Offset Bit Position 0x138 Reset Access Name Name Reset Access Description 31:24 MODCHAR12 0xFF Character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR11 0xFF...
Page 81 Reference Manual MSC - Memory System Controller 6.4.2.22 DEVINFO_MODULENAME3 - Module Name Information Offset Bit Position 0x13C Reset Access Name Name Reset Access Description 31:24 MODCHAR16 0xFF Character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR15 0xFF...
Page 82 Reference Manual MSC - Memory System Controller 6.4.2.23 DEVINFO_MODULENAME4 - Module Name Information Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:24 MODCHAR20 0xFF Character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR19 0xFF...
Page 83 Reference Manual MSC - Memory System Controller 6.4.2.24 DEVINFO_MODULENAME5 - Module Name Information Offset Bit Position 0x144 Reset Access Name Name Reset Access Description 31:24 MODCHAR24 0xFF Character of Module Name, 0xFF = unwritten, 0x00 = character not used in name 23:16 MODCHAR23 0xFF...
Page 84 Reference Manual MSC - Memory System Controller 6.4.2.26 DEVINFO_MODULEINFO - Module Information Offset Bit Position 0x14C Reset Access Name Name Reset Access Description EXTVALID EXTINFO entry used Value Mode Description EXTUSED EXTUNUSED PHYLIMITED PHY Limited Value Mode Description LIMITED UNLIMITED PADCDC PAVDD Connection Value...
Page 85 Reference Manual MSC - Memory System Controller Name Reset Access Description LFXO Factory Calibrated Value Mode Description VALID NOTVALID EXPRESS Blue Gecko Express Value Mode Description SUPPORTED NONE LFXO Module has LFXO Value Mode Description NONE PRESENT TYPE Module Type Value Mode Description...
Page 86 Reference Manual MSC - Memory System Controller 6.4.2.27 DEVINFO_MODXOCAL - Module External Oscillator Calibration Information Offset Bit Position 0x150 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 87 Reference Manual MSC - Memory System Controller 6.4.2.28 DEVINFO_HFXOCAL - High Frequency Crystal Oscillator Calibration Data Offset Bit Position 0x17C Reset Access Name Name Reset Access Description 31:8 RESERVED 0xFFFFFF New BitField Reserved VTRTRIMANA BUFOUT Reference Trim SHUNTBIASANA Shunt Regulator Bias Current Value Mode Description...
Page 88 Reference Manual MSC - Memory System Controller 6.4.2.29 DEVINFO_IADC0GAIN0 - IADC Gain Calibration Offset Bit Position 0x180 Reset Access Name Name Reset Access Description 31:16 GAINCANA2 Input Gain = 2x 15:0 GAINCANA1 Input Gain = 1x and 0.5x 6.4.2.30 DEVINFO_IADC0GAIN1 - IADC Gain Calibration Offset Bit Position 0x184...
Page 89 Reference Manual MSC - Memory System Controller 6.4.2.31 DEVINFO_IADC0OFFSETCAL0 - IADC Offset Calibration Offset Bit Position 0x188 Reset Access Name Name Reset Access Description 31:16 OFFSETANA1HIACC High-accuracy OSR adjustment term 15:0 OFFSETANABASE Base analog offset term 6.4.2.32 DEVINFO_IADC0NORMALOFFSETCAL0 - IADC Offset Calibration Offset Bit Position 0x18C...
Page 90 Reference Manual MSC - Memory System Controller 6.4.2.33 DEVINFO_IADC0NORMALOFFSETCAL1 - IADC Offset Calibration Offset Bit Position 0x190 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 91 Reference Manual MSC - Memory System Controller 6.4.2.35 DEVINFO_IADC0HISPDOFFSETCAL1 - IADC Offset Calibration Offset Bit Position 0x198 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 92 Reference Manual MSC - Memory System Controller 6.4.2.36 DEVINFO_LEGACY - Legacy Device Info Offset Bit Position 0x1FC Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 93 Reference Manual MSC - Memory System Controller Name Reset Access Description EFR32BG13B EFR32 Blue Gecko Family Series 1 Device Config 3 EFR32BG13V EFR32 Blue Gecko Family Series 1 Device Config 3 EFR32FG13P EFR32 Flex Gecko Family Series 1 Device Config 3 EFR32FG13B EFR32 Flex Gecko Family Series 1 Device Config 3 EFR32FG13V...
Page 94: Icache - Instruction Cache
Reference Manual MSC - Memory System Controller 6.4.2.37 DEVINFO_RTHERM - Offset Bit Position 0x25C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 15:0 RTHERM...
Page 95: Cache Operation
Reference Manual MSC - Memory System Controller 6.5.1 Cache Operation It is highly recommended to keep the cache enabled. To improve cache-efficiency, sections of code with very low cache hit rate should not be cached. This is achieved by placing these code sections in non-cacheable MPU regions and setting USEMPU in ICACHE_CTRL.
Page 96: Icache Register Map
Reference Manual MSC - Memory System Controller 6.5.3 ICACHE Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 ICACHE_IPVERSION IP Version 0x004 ICACHE_CTRL Control Register 0x008 ICACHE_PCHITS Performance Counter Hits 0x00C ICACHE_PCMISSES Performance Counter Misses 0x010...
Page 97: Icache Register Description
Reference Manual MSC - Memory System Controller Offset Name Type Description 0x3014 ICACHE_STATUS_TGL Status Register 0x3018 ICACHE_CMD_TGL Command Register 0x301C ICACHE_LPMODE_TGL Low Power Mode 0x3020 ICACHE_IF_TGL RWH INTFLAG Interrupt Flag 0x3024 ICACHE_IEN_TGL Interrupt Enable 6.5.4 ICACHE Register Description 6.5.4.1 ICACHE_IPVERSION - IP Version Offset Bit Position 0x000...
Page 98 Reference Manual MSC - Memory System Controller 6.5.4.2 ICACHE_CTRL - Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 99 Reference Manual MSC - Memory System Controller 6.5.4.4 ICACHE_PCMISSES - Performance Counter Misses Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:0 PCMISSES Performance Counter Misses Miss counter value 6.5.4.5 ICACHE_PCAHITS - Performance Counter Advanced Hits Offset Bit Position 0x010 Reset...
Page 100 Reference Manual MSC - Memory System Controller 6.5.4.6 ICACHE_STATUS - Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 101 Reference Manual MSC - Memory System Controller 6.5.4.8 ICACHE_LPMODE - Low Power Mode Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 102 Reference Manual MSC - Memory System Controller 6.5.4.9 ICACHE_IF - Interrupt Flag Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 103: Syscfg - System Configuration
Reference Manual MSC - Memory System Controller 6.5.4.10 ICACHE_IEN - Interrupt Enable Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 104: Ecc
Reference Manual MSC - Memory System Controller 6.6.2 ECC DMEM0, FRCRAM, and SEQRAM support one bit correction and two bit detection ECC. To enable error detection for FRCRAM and SEQRAM, set FRCRAMECCCHKEN and SEQRAMECCCHKEN in SYSCFG_RADIO- ECCCTRL. To enable auto-correction of one bit errors in FRCRAM and SEQRAM, set FRCRAMECCEWEN and SEQRAMECCEWEN in SYSCFG_RADIOECCCTRL.
Page 105: Syscfg Register Map
Reference Manual MSC - Memory System Controller 6.6.5 SYSCFG Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x004 SYSCFG_IPVERSION IP Version ID 0x008 SYSCFG_IF RWH INTFLAG Interrupt Flag 0x00C SYSCFG_IEN Interrupt Enable 0x014 SYSCFG_CHIPREVHW Chip Revision, Hard-Wired...
Page 106 Reference Manual MSC - Memory System Controller Offset Name Type Description 0x1410 SYSCFG_SEQRAMEC- SEQRAM ECC Address CADDR_SET 0x1414 SYSCFG_FRCRAMEC- FRCRAM ECC Address CADDR_SET 0x1418 SYSCFG_ICACHERAM- HOST ICACHERAM Retention Control RETNCTRL_SET 0x141C SYSCFG_DMEM0PORTMAP- DMEM0 Port Remap Selection SEL_SET 0x1600 SYSCFG_ROOTDATA0_SET Data Register 0 0x1604 SYSCFG_ROOTDATA1_SET Data Register 1...
Page 107 Reference Manual MSC - Memory System Controller Offset Name Type Description 0x3008 SYSCFG_IF_TGL RWH INTFLAG Interrupt Flag 0x300C SYSCFG_IEN_TGL Interrupt Enable 0x3014 SYSCFG_CHIPREVHW_TGL Chip Revision, Hard-Wired 0x3018 SYSCFG_CHIPREV_TGL Part Family and Revision Values 0x3024 SYSCFG_CFGSYSTIC_TGL SysTick Clock Source 0x3200 SYSCFG_CTRL_TGL Control 0x3208 SYSCFG_DMEM0RETNCTRL_T...
Page 108: Syscfg Register Description
Reference Manual MSC - Memory System Controller 6.6.6 SYSCFG Register Description 6.6.6.1 SYSCFG_IPVERSION - IP Version ID Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:0 IPVERSION New BitField ID indicating version of IP silabs.com | Building a more connected world. Rev.
Page 109 Reference Manual MSC - Memory System Controller 6.6.6.2 SYSCFG_IF - Interrupt Flag Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 110 Reference Manual MSC - Memory System Controller Name Reset Access Description Software Interrupt Flag Software interrupts Software Interrupt Flag Software interrupts Software Interrupt Flag Software interrupts Software Interrupt Flag Software interrupts silabs.com | Building a more connected world. Rev. 1.0 | 110...
Page 111 Reference Manual MSC - Memory System Controller 6.6.6.3 SYSCFG_IEN - Interrupt Enable Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 112 Reference Manual MSC - Memory System Controller Name Reset Access Description Software Interrupt Enable Set to enable the Software Interrupts Software Interrupt Enable Set to enable the Software Interrupts Software Interrupt Enable Set to enable the Software Interrupts Software Interrupt Enable Set to enable the Software Interrupts 6.6.6.4 SYSCFG_CHIPREVHW - Chip Revision, Hard-Wired Offset...
Page 113 Reference Manual MSC - Memory System Controller 6.6.6.5 SYSCFG_CHIPREV - Part Family and Revision Values Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 114 Reference Manual MSC - Memory System Controller 6.6.6.7 SYSCFG_CTRL - Control Offset Bit Position 0x200 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions RAMECCERRFAULTEN 0x1 Two bit ECC error bus fault response ena...
Page 115 Reference Manual MSC - Memory System Controller 6.6.6.8 SYSCFG_DMEM0RETNCTRL - DMEM0 Retention Control Offset Bit Position 0x208 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 116 Reference Manual MSC - Memory System Controller 6.6.6.9 SYSCFG_RAMBIASCONF - RAM Bias Configuration Offset Bit Position 0x30C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 117 Reference Manual MSC - Memory System Controller 6.6.6.10 SYSCFG_RADIORAMRETNCTRL - RADIO RAM Retention Control Register Offset Bit Position 0x400 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 118 Reference Manual MSC - Memory System Controller 6.6.6.11 SYSCFG_RADIOECCCTRL - RADIO RAM ECC Control Register Offset Bit Position 0x408 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 119 Reference Manual MSC - Memory System Controller 6.6.6.12 SYSCFG_SEQRAMECCADDR - SEQRAM ECC Address Offset Bit Position 0x410 Reset Access Name Name Reset Access Description 31:0 SEQRAMECCADDR SEQRAM ECC Address Indicates Address of SEQRAM at which ECC error occured 6.6.6.13 SYSCFG_FRCRAMECCADDR - FRCRAM ECC Address Offset Bit Position 0x414...
Page 120 Reference Manual MSC - Memory System Controller 6.6.6.14 SYSCFG_ICACHERAMRETNCTRL - HOST ICACHERAM Retention Control Offset Bit Position 0x418 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 121 Reference Manual MSC - Memory System Controller 6.6.6.15 SYSCFG_DMEM0PORTMAPSEL - DMEM0 Port Remap Selection Offset Bit Position 0x41C Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 122 Reference Manual MSC - Memory System Controller 6.6.6.17 SYSCFG_ROOTDATA1 - Data Register 1 Offset Bit Position 0x604 Reset Access Name Name Reset Access Description 31:0 DATA Data Generic data space for user to pass to root, e.g., address of struct in mem silabs.com | Building a more connected world.
Page 123 Reference Manual MSC - Memory System Controller 6.6.6.18 SYSCFG_ROOTLOCKSTATUS - Lock Status Offset Bit Position 0x608 Reset Access Name Name Reset Access Description EFUSEUNLOCKED E-Fuse Unlocked E-Fuse Unlocked when 1; Locked when 0. 30:23 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 124 Reference Manual MSC - Memory System Controller Name Reset Access Description Locked when 1; unlocked when 0. BUSLOCK Bus Lock Locked when 1; unlocked when 0. 6.6.6.19 SYSCFG_ROOTSESWVERSION - SE SW Version Offset Bit Position 0x60C Reset Access Name Name Reset Access Description...
Page 125: Mpahbram Register Map
Reference Manual MSC - Memory System Controller 6.6.7 MPAHBRAM Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MPAHBRAM_IPVERSION IP Version ID 0x004 MPAHBRAM_CMD Command Register 0x008 MPAHBRAM_CTRL Control Register 0x00C MPAHBRAM_ECCERRADDR0 ECC Error Address 0 0x010...
Page 126: Mpahbram Register Description
Reference Manual MSC - Memory System Controller Offset Name Type Description 0x3020 MPAHBRAM_IF_TGL RWH INTFLAG Interrupt Flags 0x3024 MPAHBRAM_IEN_TGL Interrupt Enable 6.6.8 MPAHBRAM Register Description 6.6.8.1 MPAHBRAM_IPVERSION - IP Version ID Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:1...
Page 127 Reference Manual MSC - Memory System Controller 6.6.8.3 MPAHBRAM_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 128 Reference Manual MSC - Memory System Controller 6.6.8.4 MPAHBRAM_ECCERRADDR0 - ECC Error Address 0 Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:0 ADDR ECC Error Address Last captured ECC error address on AHB port 0. Cleared by CMD.CLEARECCADDR0 6.6.8.5 MPAHBRAM_ECCERRADDR1 - ECC Error Address 1 Offset Bit Position...
Page 129 Reference Manual MSC - Memory System Controller 6.6.8.7 MPAHBRAM_IF - Interrupt Flags Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 130 Reference Manual MSC - Memory System Controller 6.6.8.8 MPAHBRAM_IEN - Interrupt Enable Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 131: Msc Register Map
Reference Manual MSC - Memory System Controller 6.7 MSC Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MSC_IPVERSION IP Version ID 0x004 MSC_READCTRL Read Control Register 0x008 MSC_RDATACTRL Read Data Control Register 0x00C MSC_WRITECTRL Write Control Register...
Page 132 Reference Manual MSC - Memory System Controller Offset Name Type Description 0x2004 MSC_READCTRL_CLR Read Control Register 0x2008 MSC_RDATACTRL_CLR Read Data Control Register 0x200C MSC_WRITECTRL_CLR Write Control Register 0x2010 MSC_WRITECMD_CLR Write Command Register 0x2014 MSC_ADDRB_CLR Page Erase/Write Address Buffer 0x2018 MSC_WDATA_CLR Write Data Register 0x201C MSC_STATUS_CLR Status Register...
Page 133: Msc Register Description
Reference Manual MSC - Memory System Controller 6.8 MSC Register Description 6.8.1 MSC_IPVERSION - IP Version ID Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID IP Version ID 6.8.2 MSC_READCTRL - Read Control Register Offset Bit Position 0x004...
Page 134: Msc_Rdatactrl - Read Data Control Register
Reference Manual MSC - Memory System Controller 6.8.3 MSC_RDATACTRL - Read Data Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 135: Msc_Writectrl - Write Control Register
Reference Manual MSC - Memory System Controller 6.8.4 MSC_WRITECTRL - Write Control Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 136: Msc_Writecmd - Write Command Register
Reference Manual MSC - Memory System Controller 6.8.5 MSC_WRITECMD - Write Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 137: Msc_Addrb - Page Erase/Write Address Buffer
Reference Manual MSC - Memory System Controller 6.8.6 MSC_ADDRB - Page Erase/Write Address Buffer Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:0 ADDRB Page Erase or Write Address Buffer This register holds the system address for the erase or write operation. Address should be word aligned address.The MSB bit is not ignored for ADDRB 6.8.7 MSC_WDATA - Write Data Register Offset...
Page 138: Msc_Status - Status Register
Reference Manual MSC - Memory System Controller 6.8.8 MSC_STATUS - Status Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:28 PWRUPCKBDFAIL- Flash power up checkerboard pattern chec COUNT This field tells how many times checkboard pattern check fail occured after a reset sequence. WREADY Flash Write Ready When this bit is set, flash completes the power up sequence and ready for write/erase command.
Page 139 Reference Manual MSC - Memory System Controller Name Reset Access Description When set, the current erase operation was aborted by interrupt. WDATAREADY WDATA Write Ready When this bit is set, the content of MSC_WDATA is read by MSC Flash Write Controller and the register may be updated with the next 32-bit word to be written to flash.
Page 140: Msc_Ien - Interrupt Enable Register
Reference Manual MSC - Memory System Controller 6.8.10 MSC_IEN - Interrupt Enable Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 141: Msc_Userdatasize - User Data Region Size Register
Reference Manual MSC - Memory System Controller 6.8.11 MSC_USERDATASIZE - User Data Region Size Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 142: Msc_Lock - Configuration Lock Register
Reference Manual MSC - Memory System Controller 6.8.13 MSC_LOCK - Configuration Lock Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 143: Msc_Pwrctrl - Power Control Register
Reference Manual MSC - Memory System Controller 6.8.15 MSC_PWRCTRL - Power Control Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 144: Msc_Pagelock0 - Main Space Page 0-31 Lock Word
Reference Manual MSC - Memory System Controller 6.8.16 MSC_PAGELOCK0 - Main Space Page 0-31 Lock Word Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:0 LOCKBIT page lock bit Zero means the corresponding page is allowed to write/erase. change to one will prevent corresponding page from write/ erase.
Page 145: Dbg - Debug Interface
Reference Manual DBG - Debug Interface 7. DBG - Debug Interface Quick Facts What? The Debug Interface is used to program and debug EFR32xG23 devices. Why? The Debug Interface makes it easy to re-program and update the system in the field, and allows de- bugging with minimal I/O pin usage.
Page 146: Functional Description
Reference Manual DBG - Debug Interface 7.3 Functional Description There are debug and trace pins available on the device. Operation of these pins is described in the following sections. 7.3.1 Debug Pins The following pins are the debug connections for the device: •...
Page 147: Cmu - Clock Management Unit
Reference Manual CMU - Clock Management Unit 8. CMU - Clock Management Unit Quick Facts WDOG clock What? The CMU controls clock switching and distribution. LETIMER clock EFR32xG23 supports several different oscillators with minimized power consumption and short start- RTC clock up time.
Page 148: Functional Description
Reference Manual CMU - Clock Management Unit 8.3 Functional Description The CMU is comprised of several programmable clock trees, which connect oscillator resources to peripherals and buses. This section describes clock sources and peripherals available to the largest devices in the EFR32xG23 family. Please refer to the Configuration Summary in the Device Datasheet to see which core and peripheral modules, and therefore clock connections, are present in a specific device.
Page 149 Reference Manual CMU - Clock Management Unit TRACECLK SYSCLK prescaler /1, /2, /4 CMU_TRACECLKCTRL.PRESC HFXO SYNTHCLK clock SYNTH switch CLKIN0 CMU_SYNTHCLKCTRL.CLKSEL HFRCOEM23 HFRCODPLL Availability of oscillators and clocks in Energy Modes: HFXO EM01GRPACLK TIMERn clock HFRCODPLLRT switch · Available in EM0/EM1 HFXORT ·...
Page 150 Reference Manual CMU - Clock Management Unit LFXO LFRCO clock ULFRCO WDOGnCLK switch WDOGn HCLK prescaler /1024 LFXO CMU_WDOGnCLKCTRL.CLKSEL LFXO LFRCO SYSRTCCLK clock LFRCO SYSRTC switch ULFRCO ULFRCODUTY CMU_SYSRTCCLKCTRL.CLKSEL ULFRCO LFXO EM4GRPACLK LFRCO clock BURTC switch ULFRCO Availability of oscillators and clocks in Energy Modes: CMU_EM4GRPACLKCTRL.CLKSEL ·...
Page 151: System Clocks
Reference Manual CMU - Clock Management Unit HFXO LFXO DPLLREFCLK clock DPLL switch CLKIN0 CMU_DPLLREFCLKCTRL.CLKSEL HFRCOEM23 Availability of oscillators and clocks in Energy Modes: EM01GRPCCLK clock LFXO EUSART0CLK switch · Available in EM0/EM1 EUSART0 LFRCO · Available in EM0/EM1/EM2 · Available in EM0/EM1/EM2/EM3 ·...
Page 152 Reference Manual CMU - Clock Management Unit 8.3.1.2 HCLK - AHB Clock HCLK is a prescaled version of SYSCLK. This clock drives the AHB bus interface. Example modules include the CPU, Cache, Bus Matrix, MSC, RAM, LDMA and GPIO. HCLK can be prescaled by setting HCLKPRESC in CMU_SYSCLKCTRL to DIV2 or DIV4. This prescales HCLK to all AHB bus clocks and is typically used to save energy in applications where the system is not required to run at the highest frequency.
Page 153 Reference Manual CMU - Clock Management Unit 8.3.1.9 EM4GRPACLK - Energy Mode 4 Group A Clock EM4GRPACLK is the selected clock for the Group A Peripherals operating down to Energy Mode 4. These are typically ultra low ener- gy consumption peripheral modules. There are three selectable sources for EM4GRPACLK: LFRCO, LFXO and ULFRCO. In addition, the EM4GRPACLK can be disabled.
Page 154 Reference Manual CMU - Clock Management Unit 8.3.1.16 PCNT0CLK - PCNT0 Clock PCNT0CLK is the selected clock for the PCNT peripheral. PCNT can be configured to clock from its S0 input signal, or the EM23GRPACLK, selectable by the CLKSEL field in CMU_PCNT0CLKCTRL. Note that when configured to clock from the S0 input, the clock can further be selected from the direct S0 input pin, or from a PRS channel.
Page 155: Switching Clock Source
Reference Manual CMU - Clock Management Unit 8.3.2 Switching Clock Source The FSRCO oscillator is a fixed frequency (20 MHz), low energy oscillator with extremely short start-up time. Therefore, this oscillator is chosen by hardware as the clock source for SYSCLK when the device starts up (e.g. after reset). Software can switch between the different clock sources at run-time.
Page 156 Reference Manual CMU - Clock Management Unit CMU_SYSCLKCTRL.CLKSEL HFRCO_CTRL.FORCEEN HFRCO_CTRL.DISONDEMAND HFXO_CTRL.FORCEEN HFXO_CTRL.DISONDEMAND HFRCO_STATUS.RDY HFRCO_STATUS.ENS HFXO_STATUS.RDY HFXO_STATUS.ENS BUSCLK HFRCO HFXO HFXO time-out period Figure 8.6. CMU Switching From HFRCO to HFXO After HFXO is Ready Switching clock source for various clock switches is done by setting the CLKSEL bitfields in CMU_*CLKCTRL. To ensure no stalls in the peripherals, the clock source should be ready before switching to it.
Page 157: Rc Oscillator Calibration
Reference Manual CMU - Clock Management Unit 8.3.3 RC Oscillator Calibration The CMU has built-in hardware support to efficiently calibrate RC oscillators (LFRCO, HFRCODPLL, HFRCOEM23) at run-time or measure the timing of other periodic signals routed via PRS, see Figure 8.7 Hardware Support for RC Oscillator Calibration on page for an illustration of this circuit.
Page 158 Reference Manual CMU - Clock Management Unit Up-counter sampled and CALRDY interrupt flag set. Sampled value available in CMU_CALCNT. Up-counter CALTOP Down-counter Calibration Started Calibration Stopped (counters stopped) Figure 8.8. Single Calibration (CONT=0) silabs.com | Building a more connected world. Rev.
Page 159 Reference Manual CMU - Clock Management Unit Up-counter sampled and CALRDY interrupt Up-counter sampled and CALRDY interrupt flag set. flag set. Sampled value available in CMU_CALCNT. Sampled value available in CMU_CALCNT. Up-counter CALTOP Down-counter Calibration Started Figure 8.9. Continuous Calibration (CONT=1) silabs.com | Building a more connected world.
Page 160: Energy Modes
Reference Manual CMU - Clock Management Unit 8.3.4 Energy Modes The availability of oscillators and system clocks depends on the chosen energy mode. By default, the high frequency oscillators and high frequency clocks are available down to EM1 Sleep. From EM2 DeepSleep onwards these oscillators and clocks are normally off, although special cases exist as summarized in Table 8.1 Oscillator and clock availability in Energy Modes on page 160.
Page 161: Clock Input From A Pin
Reference Manual CMU - Clock Management Unit 8.3.6 Clock Input from a Pin It is possible to configure the CMU to input a clock from the CMU_CLKI0. This clock can be selected to drive SYSCLK and DPLL refer- ence using CMU_SYSCLKCTRL.CLKSEL and CMU_DPLLREFCLKCTRL.CLKSEL respectively. The required input pin locations can be configured in the GPIO_CMU_CLKIN0ROUTE register.
Page 162: Cmu Register Map
Reference Manual CMU - Clock Management Unit 8.4 CMU Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 CMU_IPVERSION IP Version ID 0x008 CMU_STATUS Status Register 0x010 CMU_LOCK Configuration Lock Register 0x014 CMU_WDOGLOCK WDOG Configuration Lock Register...
Page 163 Reference Manual CMU - Clock Management Unit Offset Name Type Description 0x1050 CMU_CALCMD_SET Calibration Command Register 0x1054 CMU_CALCTRL_SET Calibration Control Register 0x1058 CMU_CALCNT_SET Calibration Result Counter Register 0x1064 CMU_CLKEN0_SET Clock Enable Register 0 0x1068 CMU_CLKEN1_SET Clock Enable Register 1 0x1070 CMU_SYSCLKCTRL_SET System Clock Control 0x1080...
Page 164 Reference Manual CMU - Clock Management Unit Offset Name Type Description 0x2080 CMU_TRACECLKCTRL_CLR Debug Trace Clock Control 0x2090 CMU_EXPORTCLKCTRL_CLR Export Clock Control 0x2100 CMU_DPLLREFCLKCTRL_CLR Digital PLL Reference Clock Control 0x2120 CMU_EM01GRPACLKCTRL_CL EM01 Peripheral Group a Clock Control 0x2128 CMU_EM01GRPCCLKCTRL_CL EM01 Peripheral Group C Clock Control 0x2140 CMU_EM23GRPACLKCTRL_CL EM23 Peripheral Group a Clock Control...
Page 165: Cmu Register Description
Reference Manual CMU - Clock Management Unit Offset Name Type Description 0x3128 CMU_EM01GRPCCLKCTRL_TG EM01 Peripheral Group C Clock Control 0x3140 CMU_EM23GRPACLKCTRL_TG EM23 Peripheral Group a Clock Control 0x3160 CMU_EM4GRPACLKCTRL_TGL EM4 Peripheral Group a Clock Control 0x3180 CMU_IADCCLKCTRL_TGL IADC Clock Control 0x3200 CMU_WDOG0CLKCTRL_TGL Watchdog0 Clock Control...
Page 166: Cmu_Status - Status Register
Reference Manual CMU - Clock Management Unit 8.5.2 CMU_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description LOCK Configuration Lock Status Indicates the current status of configuration lock Value Mode Description UNLOCKED Configuration lock is unlocked LOCKED Configuration lock is locked WDOGLOCK...
Page 167: Cmu_Lock - Configuration Lock Register
Reference Manual CMU - Clock Management Unit 8.5.3 CMU_LOCK - Configuration Lock Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 168: Cmu_If - Interrupt Flag Register
Reference Manual CMU - Clock Management Unit 8.5.5 CMU_IF - Interrupt Flag Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 169: Cmu_Calcmd - Calibration Command Register
Reference Manual CMU - Clock Management Unit 8.5.7 CMU_CALCMD - Calibration Command Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 170: Cmu_Calctrl - Calibration Control Register
Reference Manual CMU - Clock Management Unit 8.5.8 CMU_CALCTRL - Calibration Control Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:28 DOWNSEL Calibration Down-counter Select Selects clock source for the calibration down-counter. Changing this while calibration is running results in bus fault.. Value Mode Description...
Page 171: Cmu_Calcnt - Calibration Result Counter Register
Reference Manual CMU - Clock Management Unit Name Reset Access Description Set this bit to enable continuous calibration. Changing this while calibration is running results in bus fault. 22:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 172: Cmu_Clken0 - Clock Enable Register 0
Reference Manual CMU - Clock Management Unit 8.5.10 CMU_CLKEN0 - Clock Enable Register 0 Offset Bit Position 0x064 Reset Access Name Name Reset Access Description DCDC Enable Bus Clock Enables module PCLK/HCLK SYSRTC0 Enable Bus Clock Enables module PCLK/HCLK BURTC Enable Bus Clock Enables module PCLK/HCLK BURAM...
Page 173 Reference Manual CMU - Clock Management Unit Name Reset Access Description Enables module PCLK/HCLK DPLL0 Enable Bus Clock Enables module PCLK/HCLK SYSCFG Enable Bus Clock Enables module PCLK/HCLK I2C1 Enable Bus Clock Enables module PCLK/HCLK I2C0 Enable Bus Clock Enables module PCLK/HCLK WDOG0 Enable Bus Clock Enables module PCLK/HCLK...
Page 174: Cmu_Clken1 - Clock Enable Register 1
Reference Manual CMU - Clock Management Unit 8.5.11 CMU_CLKEN1 - Clock Enable Register 1 Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 175 Reference Manual CMU - Clock Management Unit Name Reset Access Description Enables module PCLK/HCLK ICACHE0 Enable Bus Clock Enables module PCLK/HCLK Enable Bus Clock Enables module PCLK/HCLK KEYSCAN Enable Bus Clock Enables module PCLK/HCLK Enable Bus Clock Enables module PCLK/HCLK BUFC Enable Bus Clock Enables module PCLK/HCLK...
Page 176: Cmu_Sysclkctrl - System Clock Control
Reference Manual CMU - Clock Management Unit 8.5.12 CMU_SYSCLKCTRL - System Clock Control Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 177: Cmu_Traceclkctrl - Debug Trace Clock Control
Reference Manual CMU - Clock Management Unit Name Reset Access Description Value Mode Description FSRCO FSRCO is clocking SYSCLK HFRCODPLL HFRCODPLL is clocking SYSCLK HFXO HFXO is clocking SYSCLK CLKIN0 CLKIN0 is clocking SYSCLK 8.5.13 CMU_TRACECLKCTRL - Debug Trace Clock Control Offset Bit Position 0x080...
Page 178: Cmu_Exportclkctrl - Export Clock Control
Reference Manual CMU - Clock Management Unit 8.5.14 CMU_EXPORTCLKCTRL - Export Clock Control Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 179 Reference Manual CMU - Clock Management Unit Name Reset Access Description ULFRCO ULFRCO is clocking CLKOUT1 LFRCO LFRCO is clocking CLKOUT1 LFXO LFXO is clocking CLKOUT1 HFRCODPLL HFRCODPLL is clocking CLKOUT1 HFXO HFXO is clocking CLKOUT1 FSRCO FSRCO is clocking CLKOUT1 HFRCOEM23 HFRCOEM23 is clocking CLKOUT1 Reserved...
Page 180: Cmu_Dpllrefclkctrl - Digital Pll Reference Clock Control
Reference Manual CMU - Clock Management Unit 8.5.15 CMU_DPLLREFCLKCTRL - Digital PLL Reference Clock Control Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 181: Cmu_Em01Grpaclkctrl - Em01 Peripheral Group A Clock Control
Reference Manual CMU - Clock Management Unit 8.5.16 CMU_EM01GRPACLKCTRL - EM01 Peripheral Group a Clock Control Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 182: Cmu_Em01Grpcclkctrl - Em01 Peripheral Group C Clock Control
Reference Manual CMU - Clock Management Unit 8.5.17 CMU_EM01GRPCCLKCTRL - EM01 Peripheral Group C Clock Control Offset Bit Position 0x128 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 183: Cmu_Em23Grpaclkctrl - Em23 Peripheral Group A Clock Control
Reference Manual CMU - Clock Management Unit 8.5.18 CMU_EM23GRPACLKCTRL - EM23 Peripheral Group a Clock Control Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 184: Cmu_Iadcclkctrl - Iadc Clock Control
Reference Manual CMU - Clock Management Unit 8.5.20 CMU_IADCCLKCTRL - IADC Clock Control Offset Bit Position 0x180 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 185: Cmu_Wdog1Clkctrl - Watchdog1 Clock Control
Reference Manual CMU - Clock Management Unit 8.5.22 CMU_WDOG1CLKCTRL - Watchdog1 Clock Control Offset Bit Position 0x208 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 186: Cmu_Eusart0Clkctrl - Eusart0 Clock Control
Reference Manual CMU - Clock Management Unit 8.5.23 CMU_EUSART0CLKCTRL - EUSART0 Clock Control Offset Bit Position 0x220 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 187: Cmu_Sysrtc0Clkctrl - System Rtc0 Clock Control
Reference Manual CMU - Clock Management Unit 8.5.24 CMU_SYSRTC0CLKCTRL - System RTC0 Clock Control Offset Bit Position 0x240 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 188: Cmu_Vdac0Clkctrl - Vdac0 Clock Control
Reference Manual CMU - Clock Management Unit 8.5.26 CMU_VDAC0CLKCTRL - VDAC0 Clock Control Offset Bit Position 0x260 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 189: Cmu_Pcnt0Clkctrl - Pulse Counter 0 Clock Control
Reference Manual CMU - Clock Management Unit 8.5.27 CMU_PCNT0CLKCTRL - Pulse Counter 0 Clock Control Offset Bit Position 0x270 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 190: Cmu_Lesensehfclkctrl - Lesense Hf Clock Control
Reference Manual CMU - Clock Management Unit 8.5.29 CMU_LESENSEHFCLKCTRL - LESENSE HF Clock Control Offset Bit Position 0x290 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 191: Oscillators
Reference Manual Oscillators 9. Oscillators Quick Facts What? The EFR32xG23 has a wide range of high frequency and low frequency oscillators. Why? The High Frequency oscillators support EM0/1 oper- ation. The Low-frequency oscillators provide a low frequency clock for the low energy peripherals in EM/2/3/4.
Page 192: Features
Reference Manual Oscillators 9.2.2 Features • Optimized for 39 MHz crystals • Multiple programming options of start-up parameters to enable optimization of different crystals, supporting a wide range of ESR and • Support for external sine wave input • Programmable two-phase start-up to minimize energy consumption •...
Page 193 Reference Manual Oscillators 9.2.3.3 Configuration The High Frequency Crystal Oscillator needs to be configured to ensure safe start-up for the given crystal. Refer to the Device Data sheet and application notes for guidelines in selecting correct components and crystals as well as for configuration trade-offs. The HFXO crystal is connected to the HFXTAL_I/HFXTAL_O pins as shown in Figure 9.1 HFXO Pin Connection on page 193.
Page 194 Reference Manual Oscillators 9.2.3.5 On-Demand Clocking Hardware can request to enable the HFXO by setting the HFXO_STATUS.HWREQ bit field. The HFXO can also optionally be config- ured via the HFXO_STATUS.DISONDEMAND to shut down when no hardware request is present. This is known as on-demand clock- ing and allows the oscillator to be controlled without any software intervention.
Page 195 Reference Manual Oscillators 9.2.3.9 High Frequency Clock Output (HFCLKOUT) Certain device package options include a dedicated HFCLKOUT pin. This signal is designed to be a very high quality sinusoidal clock output operating at the crystal frequency. It is suitable for driving the crystal input on other Silicon Labs EFR products, and enables multi-radio systems operating from a single crystal.
Page 196: Hfxo Register Map
Reference Manual Oscillators 9.2.4 HFXO Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 HFXO_IPVERSION IP Version ID 0x010 HFXO_XTALCFG RW SYNC Crystal Configuration Register 0x018 HFXO_XTALCTRL RWH SYNC Crystal Control Register 0x01C HFXO_XTALCTRL1 RW SYNC...
Page 197: Hfxo Register Description
Reference Manual Oscillators Offset Name Type Description 0x2058 HFXO_STATUS_CLR Status Register 0x2070 HFXO_IF_CLR RWH INTFLAG Interrupt Flag Register 0x2074 HFXO_IEN_CLR Interrupt Enable Register 0x2080 HFXO_LOCK_CLR Configuration Lock Register 0x3000 HFXO_IPVERSION_TGL IP Version ID 0x3010 HFXO_XTALCFG_TGL RW SYNC Crystal Configuration Register 0x3018 HFXO_XTALCTRL_TGL RWH SYNC...
Page 198 Reference Manual Oscillators 9.2.5.2 HFXO_XTALCFG - Crystal Configuration Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 27:24 TIMEOUTCBLSB...
Page 199 Reference Manual Oscillators Name Reset Access Description T1250US The core bias LSB change timeout is set to 1250 us minimum. The maximum can be +40%. T2083US The core bias LSB change timeout is set to 2083 us minimum. The maximum can be +40%. T3750US The core bias LSB change timeout is set to 3750 us minimum.
Page 200 Reference Manual Oscillators Name Reset Access Description 4 most significant bits of CTUNEXIANA applied during startup phase 11:6 COREBIASSTARTUP 0x20 Startup Core Bias Current 6 most significant bits of COREBIASANA applied during startup phase COREBIASSTARTUPI 0x20 Intermediate Startup Core Bias Current 6 most significant bits of COREBIASANA applied during intermediate startup phase silabs.com | Building a more connected world.
Page 201 Reference Manual Oscillators 9.2.5.3 HFXO_XTALCTRL - Crystal Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description SKIPCOREBIASOPT Skip Core Bias Optimization Set to skip the core bias current optimization algorithm at next startup. Reuse the value stored in COREBIASANA. At the successful completion of core bias current optimization algorithm, hardware sets this bit to skip optimization during sub- sequent startup.
Page 202 Reference Manual Oscillators Name Reset Access Description Approximately 10uA per step 9.2.5.4 HFXO_XTALCTRL1 - BUFOUT Crystal Control Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 203 Reference Manual Oscillators 9.2.5.5 HFXO_CFG - Configuration Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions FORCELFTIMEOUT Force Low Frequency Timeout...
Page 204 Reference Manual Oscillators 9.2.5.6 HFXO_CTRL - Control Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions DISONDEMANDBUF- Disable On-demand For BUFOUT...
Page 205 Reference Manual Oscillators Name Reset Access Description HWREQ PRS mux outputs oscillator requested by digital clock status PRSHWREQ PRS mux outputs oscillator requested by PRS request status BUFOUTHWREQ PRS mux outputs oscillator requested by BUFOUT request sta- 11:8 PRSSTATUSSEL0 PRS Status 0 Output Select Mux select for various status signals to be output through PRS.
Page 206 Reference Manual Oscillators Name Reset Access Description Upon disable, if this bit is set, analog oscillator will keep running, while clock output is shutoff. Clearing this bit has no effect until the next disable event. Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 207 Reference Manual Oscillators 9.2.5.8 HFXO_BUFOUTCTRL - BUFOUT Control Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description MINIMUMSTARTUPDE- Minimum Startup Delay If set, BUFOUT does not start until timeout expires. This prevents waste of power if BUFOUT is ready too early. 30:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un-...
Page 208 Reference Manual Oscillators Name Reset Access Description T333US The oscillator startup timeout is set to 333 us minimum. The maximum can be +40%. T375US The oscillator startup timeout is set to 375 us minimum. The maximum can be +40%. T417US The oscillator startup timeout is set to 417 us minimum.
Page 209 Reference Manual Oscillators Name Reset Access Description T938US The tuning cap change timeout is set to 938 us minimum. The maximum can be +40%. 15:12 PEAKDETTHRESANA Peak Detector Threshold for XOUT Sets the peak detector threshold for BUFOUT. Value Mode Description V105MV V132MV...
Page 210: Vdac_Outctrl - Dac Output Control
Reference Manual Oscillators 9.2.5.9 HFXO_CMD - Command Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions COREBIASOPT W(nB)
Page 211: Vdac_Outtimercfg - Dac Out Timer Config Register
Reference Manual Oscillators 9.2.5.10 HFXO_STATUS - Status Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description LOCK Configuration Lock Status Indicates the current status of configuration lock. Value Mode Description UNLOCKED Configuration lock is unlocked LOCKED Configuration lock is locked SYNCBUSY Sync Busy Indicates synchronization is ongoing.
Page 212 Reference Manual Oscillators Name Reset Access Description PRSRDY PRS Ready Status The PRS oscillator startup is ready. COREBIASOPTRDY Core Bias Optimization Ready Core bias current optimization algorithm is complete. Ready Status The digital clock branch (osc.clk_qual) is ready. silabs.com | Building a more connected world. Rev.
Page 213 Reference Manual Oscillators 9.2.5.11 HFXO_IF - Interrupt Flag Register Offset Bit Position 0x070 Reset Access Name Name Reset Access Description COREBIASOPTERR Core Bias Optimization Error Interrupt Core bias current optimization algorithm fails to complete. LFTIMEOUTERR Low Frequency Timeout Error Interrupt Low frequency timeout triggers before the steady state timeout triggers.
Page 214 Reference Manual Oscillators Name Reset Access Description Core bias current optimization algorithm is complete. Digital Clock Ready Interrupt The digital clock branch (osc.clk_qual) is ready. silabs.com | Building a more connected world. Rev. 1.0 | 214...
Page 215 Reference Manual Oscillators 9.2.5.12 HFXO_IEN - Interrupt Enable Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description COREBIASOPTERR Core Bias Optimization Error Interrupt Core bias current optimization algorithm fails to complete. LFTIMEOUTERR Low Frequency Timeout Error Interrupt Low frequency timeout triggers before the steady state timeout triggers.
Page 216: Hfrco - High-Frequency Rc Oscillator
Reference Manual Oscillators Name Reset Access Description Core bias current optimization algorithm is complete. Digital Clock Ready Interrupt The digital clock branch (osc.clk_qual) is ready. 9.2.5.13 HFXO_LOCK - Configuration Lock Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:16...
Page 217: Capacitive Sense Mode
Reference Manual Oscillators 9.3.3.2 On-Demand Clocking Hardware can request to enable the HFRCO by setting the HFRCO_STATUS.HWREQ bit field. The HFRCO can also optionally be configured via the HFRCO_STATUS.DISONDEMAND to shut down when no hardware request is present. This is known as on-demand clocking and allows the oscillator to be controlled without any software intervention.
Page 218: Output To Gpio
Reference Manual Oscillators 9.3.3.3 Calibration Several different frequencies are calibrated during production test on every device. In order to use a factory-calibrated value, software must read the value from the appropriate location in the DEVINFO page and write it to the CAL register. The TUNING and FINETUNING bit fields in the CAL register can be used to trim HFRCO manually.
Page 219 Reference Manual Oscillators 9.3.3.4 Interrupts HFRCO has one interrupt: IF.RDY. RDY is triggered when the timeout has finished and the qualified HFRCO clock is ready. The clock is gated until it is ready. 9.3.3.5 Status Flags 9.3.3.5.1 FREQBSY The FREQBSY bit indicates the HFRCO is busy updating its frequency after writing to the CAL register. The FREQBSY bit should be used whenever frequency is changed.
Page 220: Acmp_Ipversion - Ip Version
Reference Manual Oscillators 9.3.3.7 Oscillator Modes The HFRCO has three modes of operation, an on-demand mode (which is the normal software use case), a force on and a force off mode. In on-demand mode the oscillator will start whenever a peripheral requests the it. Which in most cases is whenever the module is ena- bled.
Page 221: Hfrco Register Map
Reference Manual Oscillators 9.3.4 HFRCO Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 HFRCO_IPVERSION IP Version ID 0x004 HFRCO_CTRL Ctrl Register 0x008 HFRCO_CAL RWH SYNC Calibration Register 0x00C HFRCO_STATUS Status Register 0x010 HFRCO_IF RWH INTFLAG...
Page 222: Hfrco Register Description
Reference Manual Oscillators 9.3.5 HFRCO Register Description 9.3.5.1 HFRCO_IPVERSION - IP Version ID Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 223 Reference Manual Oscillators 9.3.5.3 HFRCO_CAL - Calibration Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:28 IREFTC Tempco Trim on Comparator Current Writing this field adjusts the temperature coefficient trim on comparator current. 27:26 CMPSEL Comparator Load Select Writing this field adjusts the active load for comparators.
Page 224: Acmp_Inputctrl - Input Control Register
Reference Manual Oscillators 9.3.5.4 HFRCO_STATUS - Status Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description LOCK Lock Status If set, all HFRCO lockable registers are locked. Value Mode Description UNLOCKED HFRCO is unlocked LOCKED HFRCO is locked 30:17 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un-...
Page 225 Reference Manual Oscillators 9.3.5.5 HFRCO_IF - Interrupt Flag Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions Ready Interrupt Flag Set when HFRCO is ready (start-up time exceeded).
Page 226: Dpll - Digital Phased Locked Loop
Reference Manual Oscillators 9.3.5.7 HFRCO_LOCK - Lock Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 15:0 LOCKKEY...
Page 227 Reference Manual Oscillators 9.4.3.1 Enabling and Disabling The DPLL can be enabled and disabled by software via the DPLL_EN register. Before enabling DPLL, software should: 1. Select reference clock by setting the CLKSEL field in CMU_DPLLREFCLKCTRL. 2. The CMU should not be running from the HFRCO. If necessary, the CMU should switch to the FSRCO until after the DPLL has locked to avoid over-clocking due to overshoot.
Page 228: Dpll Register Map
Reference Manual Oscillators 9.4.4 DPLL Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DPLL_IPVERSION IP Version 0x004 DPLL_EN RW ENABLE Enable 0x008 DPLL_CFG RW CONFIG Config 0x00C DPLL_CFG1 RW CONFIG Config1 0x010 DPLL_IF...
Page 229: Dpll Register Description
Reference Manual Oscillators 9.4.5 DPLL Register Description 9.4.5.1 DPLL_IPVERSION - IP Version Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 230 Reference Manual Oscillators 9.4.5.3 DPLL_CFG - Config Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:7 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions DITHEN Dither Enable Control...
Page 231: Acmp_Ien - Interrupt Enable Register
Reference Manual Oscillators 9.4.5.4 DPLL_CFG1 - Config1 Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 27:16 Factor N...
Page 232 Reference Manual Oscillators 9.4.5.6 DPLL_IEN - Interrupt Enable Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions LOCKFAILHIGH LOCKFAILHIGH Interrupt Enable...
Page 233 Reference Manual Oscillators 9.4.5.7 DPLL_STATUS - Status Offset Bit Position 0x018 Reset Access Name Name Reset Access Description LOCK Lock Status Indicates the current status of configuration lock Value Mode Description UNLOCKED DPLL is unlocked LOCKED DPLL is locked 30:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 234: Lfxo - Low-Frequency Crystal Oscillator
Reference Manual Oscillators 9.5 LFXO - Low-Frequency Crystal Oscillator 9.5.1 Introduction The Low Frequency Crystal Oscillator (LFXO) uses an external 32.768 kHz crystal to provide an accurate low-frequency clock. The module is available in all energy modes, except EM3. The main interaction is with the CMU through the clock requesting mechanism. 9.5.2 Features High-level features.
Page 235 Reference Manual Oscillators 9.5.3.4 Edge Detection Interrupts There is a possibility for software to detect rising or falling edges of the LFXO clock. The edge detection is enabled if any of POSEDG- EIEN and NEGEDGEIEN is set to 1. The corresponding flags are available in POSEDGEIF and NEGEDGEIF. If none of the interrupts are enabled, the edge detection is disabled and POSEDGEIF and NEGEDGEIF hold their last value until cleared or set by software.
Page 236: Lfxo Register Map
Reference Manual Oscillators 9.5.4 LFXO Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LFXO_IPVERSION LFXO IP Version 0x004 LFXO_CTRL LFXO Control Register 0x008 LFXO_CFG LFXO Configuration Register 0x010 LFXO_STATUS LFXO Status Register 0x014 LFXO_CAL RW LFSYNC...
Page 237: Lfxo Register Description
Reference Manual Oscillators Offset Name Type Description 0x3024 LFXO_LOCK_TGL Configuration Lock Register 9.5.5 LFXO Register Description 9.5.5.1 LFXO_IPVERSION - LFXO IP Version Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 238 Reference Manual Oscillators 9.5.5.2 LFXO_CTRL - LFXO Control Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions FAILDETEM4WUEN LFXO Failure Detection EM4WU Enable...
Page 239 Reference Manual Oscillators 9.5.5.3 LFXO_CFG - LFXO Configuration Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 10:8 TIMEOUT...
Page 240: Keyscan_Cmd - Command
Reference Manual Oscillators Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions HIGHAMPL LFXO High Amplitude Enable Set this bit to enable high XTAL oscillation amplitude. LFXO AGC Enable Set this bit to enable automatic gain control which limits XTAL oscillation amplitude.
Page 241 Reference Manual Oscillators 9.5.5.5 LFXO_CAL - LFXO Calibration Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions GAIN LFXO Startup Gain...
Page 242 Reference Manual Oscillators 9.5.5.6 LFXO_IF - Interrupt Flag Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions FAIL LFXO Failure Interrupt Flag...
Page 243 Reference Manual Oscillators 9.5.5.7 LFXO_IEN - Interrupt Enable Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions FAIL LFXO Failure Interrupt Enable...
Page 244: Lfrco - Low-Frequency Rc Oscillator
Reference Manual Oscillators 9.5.5.9 LFXO_LOCK - Configuration Lock Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 15:0 LOCKKEY...
Page 245 Reference Manual Oscillators 9.6.3.2 On-Demand Clocking Hardware can request to enable the LFRCO by setting the LFRCO_STATUS.HWREQ bit field. The LFRCO can also optionally be con- figured via the LFRCO_STATUS.DISONDEMAND to shut down when no hardware request is present. This is known as on-demand clocking and allows the oscillator to be controlled without any software intervention.
Page 246: Lfrco Register Map
Reference Manual Oscillators 9.6.4 LFRCO Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LFRCO_IPVERSION IP Version 0x004 LFRCO_CTRL Control Register 0x008 LFRCO_STATUS Status Register 0x00C LFRCO_CAL Calibration Register 0x014 LFRCO_IF RWH INTFLAG Interrupt Flag Register 0x018...
Page 247: Lfrco Register Description
Reference Manual Oscillators 9.6.5 LFRCO Register Description 9.6.5.1 LFRCO_IPVERSION - IP Version Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 248 Reference Manual Oscillators 9.6.5.3 LFRCO_STATUS - Status Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description LOCK Lock Status This bit is set when LFRCO is locked. Value Mode Description UNLOCKED Access to configuration registers not locked LOCKED Access to configuration registers locked 30:17...
Page 249 Reference Manual Oscillators 9.6.5.5 LFRCO_IF - Interrupt Flag Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions NEGEDGE Falling Edge Interrupt Flag...
Page 250: Fsrco - Fast Start Rco
Reference Manual Oscillators 9.6.5.7 LFRCO_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions CAL Busy CAL register synchronization busy bit...
Page 251: Features
Reference Manual Oscillators 9.7.2 Features • 20 MHz nominal frequency • Low energy consumption 9.7.3 Functional Description There are no programmable registers in this module. Software can choose to use this as system clock in the CMU block. the only way to enable or disable the FSRCO is by requesting it as a clock source in the CMU clock select registers.
Page 252: Functional Description
Reference Manual Oscillators 9.8.3 Functional Description There are no user programmable registers in this module. The oscillator is always on in all energy modes except EM4. In EM4, the oscillator is available on-demand by peripheral requests. silabs.com | Building a more connected world. Rev.
Page 253: Smu - Security Management Unit
Reference Manual SMU - Security Management Unit 10. SMU - Security Management Unit Quick Facts What? The Security Management Unit (SMU) provides con- figuration and status reporting for ARM TrustZone on the EFR32xG23. Why? Enables a robust solution at the system level. How? Hardware context switching and enhanced security provided by ARM TrustZone.
Page 254: Functional Description
Reference Manual SMU - Security Management Unit 10.3 Functional Description 10.3.1 Bus Level Security Bus level security is the ability to control the flow of information on the device. The components of bus level security are the Cortex- M33, the Bus Manager Protect Unit (BMPU), and the Peripheral Protection Unit (PPU) as highlighted in Figure 10.1 Bus Level Security Implementation on page 254.
Page 255: Privileged Access Control
Reference Manual SMU - Security Management Unit 10.3.2 Privileged Access Control The Cortex-M33 and all other managers can be in either the privileged or unprivileged state. All bus access to peripherals are tested for privilege level by the PPU and resolved as shown in Table 10.1 Privileged Access Table on page 255.
Page 256: Arm Trustzone
Reference Manual SMU - Security Management Unit 10.3.4 ARM TrustZone ARM TrustZone is used to control what addresses are accessible by the CPU at any given time. There are two security states: secure and non-secure. In addition the MPU provides two privilege levels: privileged and unprivileged. This results in 4 possible states: secure- privileged, non-secure-privileged, secure-unprivileged and non-secure-unprivileged.
Page 257: Configuring Memory
Reference Manual SMU - Security Management Unit 10.3.7 Configuring Memory The SMU provides the ability to configure the security attribute of memory. There are 13 configurable regions in total. There are three regions in FLASH (0 - 2) and three in RAM (4-6) which have pre-determined secure attributes and user selectable sizes. Regions 3 and 11 cover the flash info page and ARM EPPB space respectively and have a fixed size.
Page 258: Exception Handling
Reference Manual SMU - Security Management Unit 10.3.9 Exception Handling When a BMPU detects a non-secure manager attempting to access a secure address, the BMPUSECIF in SMU_IF is set and the ID of the Manager block is written to SMU_BMPUFS. If BMPUSECIEN is set and the SMU's Secure IRQ enabled, the CPU will be interrup- ted.
Page 259: Smu Register Map
Reference Manual SMU - Security Management Unit 10.4 SMU Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 SMU_IPVERSION IP Version 0x004 SMU_STATUS Status Register 0x008 SMU_LOCK Lock Register 0x00C SMU_IF RWH INTFLAG Interrupt Flag Register 0x010...
Page 260 Reference Manual SMU - Security Management Unit Offset Name Type Description 0x1254 SMU_BMPUFSADDR_SET Fault Status Address 0x1260 SMU_ESAURTYPES0_SET Region Types 0 0x1264 SMU_ESAURTYPES1_SET Region Types 1 0x1270 SMU_ESAUMRB01_SET Movable Region Boundary 0x1274 SMU_ESAUMRB12_SET Movable Region Boundary 0x1280 SMU_ESAUMRB45_SET Movable Region Boundary 0x1284 SMU_ESAUMRB56_SET Movable Region Boundary...
Page 261: Smu Register Description
Reference Manual SMU - Security Management Unit Offset Name Type Description 0x3064 SMU_PPUSATD1_TGL Secure Access 0x3140 SMU_PPUFS_TGL Fault Status 0x3150 SMU_BMPUPATD0_TGL Privileged Attribute 0x3170 SMU_BMPUSATD0_TGL Secure Attribute 0x3250 SMU_BMPUFS_TGL Fault Status 0x3254 SMU_BMPUFSADDR_TGL Fault Status Address 0x3260 SMU_ESAURTYPES0_TGL Region Types 0 0x3264 SMU_ESAURTYPES1_TGL Region Types 1...
Page 262: Smu_Status - Status Register
Reference Manual SMU - Security Management Unit 10.5.2 SMU_STATUS - Status Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 263: Smu_If - Interrupt Flag Register
Reference Manual SMU - Security Management Unit 10.5.4 SMU_IF - Interrupt Flag Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 264: Smu_Ien - Interrupt Enable Register
Reference Manual SMU - Security Management Unit 10.5.5 SMU_IEN - Interrupt Enable Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 265: Smu_M33Ctrl - M33 Control Settings
Reference Manual SMU - Security Management Unit 10.5.6 SMU_M33CTRL - M33 Control Settings Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 266: Smu_Ppupatd0 - Privileged Access
Reference Manual SMU - Security Management Unit 10.5.7 SMU_PPUPATD0 - Privileged Access Offset Bit Position 0x040 Reset Access Name Name Reset Access Description EUSART2 EUSART2 Privileged Access EUSART2 Privileged Access EUSART1 EUSART1 Privileged Access EUSART1 Privileged Access HOSTMAILBOX HOSTMAILBOX Privileged Access HOSTMAILBOX Privileged Access DCDC DCDC Privileged Access...
Page 267 Reference Manual SMU - Security Management Unit Name Reset Access Description TIMER3 Privileged Access TIMER2 TIMER2 Privileged Access TIMER2 Privileged Access TIMER1 TIMER1 Privileged Access TIMER1 Privileged Access TIMER0 TIMER0 Privileged Access TIMER0 Privileged Access LDMAXBAR LDMAXBAR Privileged Access LDMAXBAR Privileged Access LDMA LDMA Privileged Access LDMA Privileged Access...
Page 268: Smu_Ppupatd1 - Privileged Access
Reference Manual SMU - Security Management Unit 10.5.8 SMU_PPUPATD1 - Privileged Access Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 269 Reference Manual SMU - Security Management Unit Name Reset Access Description ACMP0 ACMP0 Privileged Access ACMP0 Privileged Access IADC0 IADC0 Privileged Access IADC0 Privileged Access LETIMER0 LETIMER0 Privileged Access LETIMER0 Privileged Access SMUCFGNS SMUCFGNS Privileged Access SMUCFGNS Privileged Access SMU Privileged Access SMU Privileged Access RADIOAES RADIOAES Privileged Access...
Page 270: Smu_Ppusatd0 - Secure Access
Reference Manual SMU - Security Management Unit 10.5.9 SMU_PPUSATD0 - Secure Access Offset Bit Position 0x060 Reset Access Name Name Reset Access Description EUSART2 EUSART2 Secure Access EUSART2 Secure Access EUSART1 EUSART1 Secure Access EUSART1 Secure Access HOSTMAILBOX HOSTMAILBOX Secure Access HOSTMAILBOX Secure Access DCDC DCDC Secure Access...
Page 271 Reference Manual SMU - Security Management Unit Name Reset Access Description TIMER3 Secure Access TIMER2 TIMER2 Secure Access TIMER2 Secure Access TIMER1 TIMER1 Secure Access TIMER1 Secure Access TIMER0 TIMER0 Secure Access TIMER0 Secure Access LDMAXBAR LDMAXBAR Secure Access LDMAXBAR Secure Access LDMA LDMA Secure Access LDMA Secure Access...
Page 272: Smu_Ppusatd1 - Secure Access
Reference Manual SMU - Security Management Unit 10.5.10 SMU_PPUSATD1 - Secure Access Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 273 Reference Manual SMU - Security Management Unit Name Reset Access Description ACMP0 ACMP0 Secure Access ACMP0 Secure Access IADC0 IADC0 Secure Access IADC0 Secure Access LETIMER0 LETIMER0 Secure Access LETIMER0 Secure Access SMUCFGNS SMUCFGNS Secure Access SMUCFGNS Secure Access SMU Secure Access SMU Secure Access RADIOAES RADIOAES Secure Access...
Page 274: Smu_Ppufs - Fault Status
Reference Manual SMU - Security Management Unit 10.5.11 SMU_PPUFS - Fault Status Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 275: Smu_Bmpupatd0 - Privileged Attribute
Reference Manual SMU - Security Management Unit 10.5.12 SMU_BMPUPATD0 - Privileged Attribute Offset Bit Position 0x150 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 276: Smu_Bmpusatd0 - Secure Attribute
Reference Manual SMU - Security Management Unit 10.5.13 SMU_BMPUSATD0 - Secure Attribute Offset Bit Position 0x170 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 277: Smu_Bmpufs - Fault Status
Reference Manual SMU - Security Management Unit 10.5.14 SMU_BMPUFS - Fault Status Offset Bit Position 0x250 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 278: Smu_Esaurtypes0 - Region Types 0
Reference Manual SMU - Security Management Unit 10.5.16 SMU_ESAURTYPES0 - Region Types 0 Offset Bit Position 0x260 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 279: Smu_Esaumrb01 - Movable Region Boundary
Reference Manual SMU - Security Management Unit 10.5.18 SMU_ESAUMRB01 - Movable Region Boundary Offset Bit Position 0x270 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 280: Smu_Esaumrb45 - Movable Region Boundary
Reference Manual SMU - Security Management Unit 10.5.20 SMU_ESAUMRB45 - Movable Region Boundary Offset Bit Position 0x280 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 281: Se - Secure Engine Subsystem
Reference Manual SE - Secure Engine Subsystem 11. SE - Secure Engine Subsystem Quick Facts What? The Secure Engine Subsystem encapsulates securi- ty peripherals providing both improved system se- curity and ease of use. Why? Isolation of security hardware from the Cortex-M33 protects the SE system from exploits that target the main CPU.
Page 282: Secure Boot With Root Of Trust And Secure Loader (Rtsl)
Reference Manual SE - Secure Engine Subsystem 11.2.2 Secure Boot with Root of Trust and Secure Loader (RTSL) The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM). It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed, and protects Over The Air updates. For more information about this feature, see AN1218: Series 2 Secure Boot with RTSL.
Page 283: True Random Number Generation
Reference Manual SE - Secure Engine Subsystem 11.2.5 True Random Number Generation The SE provides access to a non-deterministic random number generator based on a full hardware solution. The TRNG output passes the NIST 800-22 and AIS31 test suites. The TRNG module includes several built-in self tests to detect issues with the noise source, ensure entropy, and meet cryptography standards.
Page 284: Mailbox Register Map
Reference Manual SE - Secure Engine Subsystem 11.3.3 MAILBOX Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 MAILBOX_MSGPTRx Message Pointer 0x040 MAILBOX_IF RW INTFLAG Interrupt Flag Register 0x044 MAILBOX_IEN Interrupt Enable Register 0x1000 MAILBOX_MSGPTRx_SET Message Pointer...
Page 285 Reference Manual SE - Secure Engine Subsystem 11.3.4.2 MAILBOX_IF - Interrupt Flag Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 286 Reference Manual SE - Secure Engine Subsystem 11.3.4.3 MAILBOX_IEN - Interrupt Enable Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 287: Emu - Energy Management Unit
Reference Manual EMU - Energy Management Unit 12. EMU - Energy Management Unit Quick Facts What? The EMU (Energy Management Unit) handles the different low energy modes in EFR32xG23 Why? The need for performance and peripheral functions varies over time in most applications. By efficiently scaling the available resources in real time to match the demands of the application, the energy con- sumption can be kept at a minimum.
Page 288: Features
Reference Manual EMU - Energy Management Unit 12.2 Features The primary features of the EMU are listed below: • Energy Modes control • Entry into EM4 • Configuration of regulators and clocks for each Energy Mode • Configuration of various EM4 wake-up conditions •...
Page 289: Functional Description
Reference Manual EMU - Energy Management Unit 12.3 Functional Description The EMU is responsible for managing the wide range of energy modes available in EFR32xG23. The block works in harmony with the entire platform to easily transition between energy modes in the most efficient manner possible. The following diagram Figure 12.1 EMU Overview on page 289, shows the relative connectivity to the various blocks in the system.
Page 290: Energy Modes
Reference Manual EMU - Energy Management Unit 12.3.1 Energy Modes EFR32xG23 features five main energy modes, referred to as Energy Mode 0 ( EM0) through Energy Mode 4 (EM4). The Cortex-M33 is only available for program execution in EM0. In EM0 Active/EM1 Sleep any peripheral function can be enabled. EM2 through EM4, also referred to as low energy modes, provide a significantly reduced energy consumption while still allowing a rich set of peripheral func- tionality.
Page 291 Reference Manual EMU - Energy Management Unit EM0 / EM1 Fast Startup RC Oscillator Available Available Available (FSRCO), EM2/3 High Fre- quency Oscillator (HFRCOEM23), ADC Clock (IADCCLK), and VDAC0 Clock (VDAC0CLK) Low Frequency Oscillators Available Available Available (LFRCO, LFXO) Low Energy Clocks Available Available Available...
Page 292 Reference Manual EMU - Energy Management Unit EM0 / EM1 PRS (Peripheral Reflex Sys- Available Available Available tem) GPIO Pin Interrupts Available Available Available Available GPIO Pin State Retention Available Note: 1. Leaving the debugger connected when in EM2 or EM3 will cause the system to enter a higher power EM2 mode in which the high frequency clocks are still enabled and certain core functionality is still powered-up in order to maintain debug-functionality.
Page 293 Reference Manual EMU - Energy Management Unit 12.3.1.4 EM2 This is the first level into the low power energy modes. Most of the high frequency peripherals are disabled or have reduced functionali- ty. Memory and registers retain their values. • Cortex-M33 is in sleep mode. Clocks to the core are off. •...
Page 294: Entering Low Energy Modes
Reference Manual EMU - Energy Management Unit 12.3.1.6 EM4 EM4 is the lowest energy mode of the part. There is no retention except for GPIO PAD state and BURAM values. Wake-up from EM4 requires a reset to the system, returning it back to EM0 •...
Page 295: Exiting A Low Energy Mode
Reference Manual EMU - Energy Management Unit 12.3.2.3 Entry Into EM4 Energy mode EM4 is entered through register access. Software must ensure no modules are active, such as the Radio, when entering EM4. Software may enter EM4 from EM0 by writing the sequence 2,3,2,3,2,3,2,3,2 to EM4CTRL->EM4ENTRY bit field. If the EM4BLOCK bit in WDOGn_CTRL is set, the CPU will be prevented from entering EM4 by software request.
Page 296: Power Domains
Reference Manual EMU - Energy Management Unit 12.3.4 Power Domains The EFR32xG23 implements several independent power domains which are powered down to minimize supply current when not in use. Power domains are managed automatically by the EMU. The lowest-energy power domain is the "high-voltage" power domain (PDHV), which supports extremely low-energy infrastructure and peripherals.
Page 297: Em0 / Em1 Peripheral Register Retention
Reference Manual EMU - Energy Management Unit 12.3.5.2 Voltage Scaling in EM2 and EM3 A separate voltage scaling value is used during EM2 and EM3. This allows the core to run at a higher voltage when in EM0 / EM1 and reduce the voltage in EM2 and EM3 for power savings.
Page 298 Reference Manual EMU - Energy Management Unit 12.3.7.1 Power Configuration 0: STARTUP Upon power-on reset (POR), the system is configured in a safe Startup Configuration that supports all of the available Power Configura- tions. The Startup Configuration is shown in the simplified diagram below. In the Startup configuration the DC-DC converter's Bypass switch is ON (i.e., the VREGVDD pin is shorted internally to the DVDD pin).
Page 299 Reference Manual EMU - Energy Management Unit 12.3.7.2 Power Configuration 1: No DC-DC In Power Configuration 1, the DC-DC converter is unused, and all power is supplied by external sources. The DVDD pin must be shor- ted to VREGVDD. Other supplies may be supplied by the same supply as VREGIN and DVDD (as shown in 12.3.7.2 Power Configuration 1: No DC-DC), or they may be powered from a separate source.
Page 300 Reference Manual EMU - Energy Management Unit 12.3.7.3 Power Configuration 2: DC-DC For the lowest power applications, the DC-DC converter can be used to power the rest of the supplies on the device. When the DC-DC converter is used to regulate the voltage at DVDD, the maximum supply voltage may be limited by the operating temperature and/or the average lifetime load conditions.
Page 301: Buck Dc-Dc Interface
Reference Manual EMU - Energy Management Unit 12.3.7.4 Power Configuration 3: DC-DC With Separate PAVDD For power-conscious applications that require higher RF transmitter output power (> 14 dBm), PAVDD may be powered from the sys- tem supply, while the DC-DC converter can be used to power other supplies on the device. This situation is very similar to 12.3.7.3 Power Configuration 2: DC-DC, but PAVDD has been separated out to achieve higher transmitter power.
Page 302 Reference Manual EMU - Energy Management Unit 12.3.8.1 Buck DC-DC Mode Bypass and VREGVDD Comparator The buck DC-DC converter implements a bypass mode which shorts the VREGVDD input voltage directly to the DC-DC converter out- put through an internal switch. Bypass mode is enabled automatically during a power-on-reset. Bypass mode can also be enabled and disabled through software, using the DCDC_CTRL_MODE field.
Page 303 Reference Manual EMU - Energy Management Unit 12.3.8.3 Buck DC-DC Recommended Configuration Settings Certain DC-DC parameters are adjustable for fine-tuning of performance, but the majority of applications will not need to use any other than the recommended settings. All datasheet parameters are specified using the recommended settings detailed in this section. The configuration settings must be set before DC-DC regulation is started, and must not be changed while the DC-DC is active.
Page 304: Efp01 Communication
Reference Manual EMU - Energy Management Unit 12.3.9 EFP01 Communication The EFP01 Energy Friendly Power Management IC (PMIC) is an extremely flexible, highly efficient, multi-output power management IC, providing complete system power and primary cell battery Coulomb counting for EFR32xG23 devices. The dual-DCDC converter outputs available on certain EFP01 OPNs can, for example, provide power to both the 1.8 V supplies (e.g., DVDD/AVDD/IOVDD) as well as the 1.1/1.0/0.9 V supply (DECOUPLE) for improved efficiency.
Page 305: Brown Out Detector (Bod)
Reference Manual EMU - Energy Management Unit To enable Direct Mode: 1. The I2C1 module must be used to communicate with EFP01. I2C0 is not supported. 2. The I2C1_SDA function must be routed to the PC1 pin and connected on the PCB to EFP01's I2C_SDA pin. 3.
Page 306: Reset Management Unit
Reference Manual EMU - Energy Management Unit 12.3.11 Reset Management Unit EMU RMU (Reset Management Unit) ensures correct reset operation. It is responsible for connecting the different reset sources to the reset lines of the EFR32xG23. After reset, the M33 loads the stack pointer and program entry point from memory and start execution. Secure Tamper Detect Engine...
Page 307 Reference Manual EMU - Energy Management Unit EFR32xG23 Reset sources • Power-on Reset (POR) • The POR ensures that EFR32xG23 does not start up before the supply voltage DVDD has reached the threshold voltage VPORthr (see Device Datasheet Electrical Characteristics for details). Before the threshold voltage is reached, EFR32xG23 is kept in reset state.
Page 308: Temperature Sensor
Reference Manual EMU - Energy Management Unit 12.3.12 Temperature Sensor EMU provides a low energy periodic temperature measurement. A temperature measurement is taken once every 250 ms, with the 9- bit result stored in TEMP bit-field in EMU_TEMP register. The temperature value is expressed in degrees Kelvin. EMU_TEMP_TEMPLSB represents the measured temperature fractional part (in ¼...
Page 309: Register Resets
Reference Manual EMU - Energy Management Unit 12.3.13 Register Resets Each EMU register requires retaining state in various energy modes and power transitions and will consequently need to be reset with a different condition. The following reset conditions will apply to the appropriate set of registers as marked in the Register Description table.
Page 310: Emu Register Map
Reference Manual EMU - Energy Management Unit 12.4 EMU Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x010 EMU_DECBOD DECOUPLE LVBOD Control Register 0x020 EMU_BOD3SENSE BOD3SENSE Control Register 0x03C EMU_VREGVDDCMPCTRL DC-DC VREGVDD Comparator Control Register 0x040 EMU_PD1PARETCTRL PD1 Partial Retention Control...
Page 311 Reference Manual EMU - Energy Management Unit Offset Name Type Description 0x1090 EMU_RSTCTRL_SET Reset Management Control Register 0x1094 EMU_RSTCAUSE_SET Reset Cause 0x10A0 EMU_DGIF_SET RWH INTFLAG Interrupt Flags Debug 0x10A4 EMU_DGIEN_SET Interrupt Enables Debug 0x1100 EMU_EFPIF_SET RWH INTFLAG EFP Interrupt Register 0x1104 EMU_EFPIEN_SET EFP Interrupt Enable Register...
Page 312: Emu Register Description
Reference Manual EMU - Energy Management Unit Offset Name Type Description 0x3074 EMU_CTRL_TGL EMU Control Register 0x3078 EMU_TEMPLIMITS_TGL EMU Temperature Thresholds 0x3084 EMU_STATUS_TGL EMU Status Register 0x3088 EMU_TEMP_TGL Temperature 0x3090 EMU_RSTCTRL_TGL Reset Management Control Register 0x3094 EMU_RSTCAUSE_TGL Reset Cause 0x30A0 EMU_DGIF_TGL RWH INTFLAG Interrupt Flags Debug...
Page 313: Emu_Bod3Sense - Bod3Sense Control Register
Reference Manual EMU - Energy Management Unit 12.5.2 EMU_BOD3SENSE - BOD3SENSE Control Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 314: Emu_Pd1Paretctrl - Pd1 Partial Retention Control
Reference Manual EMU - Energy Management Unit 12.5.4 EMU_PD1PARETCTRL - PD1 Partial Retention Control Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 315: Emu_Lock - Emu Configuration Lock Register
Reference Manual EMU - Energy Management Unit 12.5.6 EMU_LOCK - EMU Configuration Lock Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 316: Emu_If - Interrupt Flags
Reference Manual EMU - Energy Management Unit 12.5.7 EMU_IF - Interrupt Flags Offset Bit Position 0x064 Reset Access Name Name Reset Access Description TEMPHIGH Temperature high Interrupt flag Measured temperature above threshold TEMPLOW Temperature low Interrupt flag Measured temperature below threshold TEMP Temperature Interrupt flag Temperature Update...
Page 317: Emu_Ien - Interrupt Enables
Reference Manual EMU - Energy Management Unit 12.5.8 EMU_IEN - Interrupt Enables Offset Bit Position 0x068 Reset Access Name Name Reset Access Description TEMPHIGH Temperature high Interrupt enable Measured temperature above threshold Interrupt enable TEMPLOW Temperature low Interrupt enable Measured temperature below threshold Interrupt enable TEMP Temperature Interrupt enable Temperature Update Interrupt enable...
Page 318: Emu_Em4Ctrl - Em4 Control
Reference Manual EMU - Energy Management Unit 12.5.9 EMU_EM4CTRL - EM4 Control Offset Bit Position 0x06C Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 319: Emu_Cmd - Emu Command Register
Reference Manual EMU - Energy Management Unit 12.5.10 EMU_CMD - EMU Command Register Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 320: Emu_Ctrl - Emu Control Register
Reference Manual EMU - Energy Management Unit 12.5.11 EMU_CTRL - EMU Control Register Offset Bit Position 0x074 Reset Access Name Name Reset Access Description EFPDRVDVDD EFP drives DVDD EFP01 Drives DVDD. EFP IRQ is enabled on PC5. VREGVDD and DVDD pins should be shorted together on the PCB. EFPDRVDECOUPLE EFP drives DECOUPLE EFP01 Drives DECOUPLE.
Page 321: Emu_Templimits - Emu Temperature Thresholds
Reference Manual EMU - Energy Management Unit Name Reset Access Description Value Mode Description 16 measurements 64 measurements Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions EM2DBGEN Enable debugging in EM2...
Page 322: Emu_Status - Emu Status Register
Reference Manual EMU - Energy Management Unit 12.5.13 EMU_STATUS - EMU Status Register Offset Bit Position 0x084 Reset Access Name Name Reset Access Description 31:15 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 323: Emu_Temp - Temperature
Reference Manual EMU - Energy Management Unit Name Reset Access Description Temperature Measurement active FIRSTTEMPDONE First Temp done First Temperatue mesaurement completed LOCK Lock status Indicates the current status of EMU Lock Value Mode Description UNLOCKED All EMU lockable registers are unlocked. LOCKED All EMU lockable registers are locked.
Page 324: Emu_Rstctrl - Reset Management Control Register
Reference Manual EMU - Energy Management Unit 12.5.15 EMU_RSTCTRL - Reset Management Control Register Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 325 Reference Manual EMU - Energy Management Unit Name Reset Access Description ENABLED The entire device is reset except some EMU registers SYSRMODE Enable M33 System reset Core Sysreset Reset Mode Value Mode Description DISABLED Reset request is blocked ENABLED Device is reset except some EMU registers Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 326: Emu_Rstcause - Reset Cause
Reference Manual EMU - Energy Management Unit 12.5.16 EMU_RSTCAUSE - Reset Cause Offset Bit Position 0x094 Reset Access Name Name Reset Access Description VREGIN DCDC VREGIN comparator DCDC VREGIN comparator below threshold. For Information only, not a direct source for reset. Should be used to deter- mine whether the previous reset was caused by DCDC input being too low to support current load.
Page 327: Emu_Dgif - Interrupt Flags Debug
Reference Manual EMU - Energy Management Unit Name Reset Access Description Last reset was a Power On Reset 12.5.17 EMU_DGIF - Interrupt Flags Debug Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description TEMPHIGHDGIF Temperature high Interrupt flag Measured temperature above threshold TEMPLOWDGIF Temperature low Interrupt flag...
Page 328: Emu_Dgien - Interrupt Enables Debug
Reference Manual EMU - Energy Management Unit 12.5.18 EMU_DGIEN - Interrupt Enables Debug Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description TEMPHIGHDGIEN Temperature high Interrupt enable Measured temperature above threshold TEMPLOWDGIEN Temperature low Interrupt enable Measured temperature below threshold TEMPDGIEN Temperature Interrupt enable Temperature Update...
Page 329: Emu_Efpien - Efp Interrupt Enable Register
Reference Manual EMU - Energy Management Unit 12.5.20 EMU_EFPIEN - EFP Interrupt Enable Register Offset Bit Position 0x104 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 330: Dcdc Register Map
Reference Manual EMU - Energy Management Unit 12.6 DCDC Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 DCDC_IPVERSION IPVERSION 0x004 DCDC_CTRL RW SYNC Control 0x008 DCDC_EM01CTRL0 RW SYNC EM01 Control 0x010 DCDC_EM23CTRL0 RW SYNC...
Page 331: Dcdc Register Description
Reference Manual EMU - Energy Management Unit Offset Name Type Description 0x3008 DCDC_EM01CTRL0_TGL RW SYNC EM01 Control 0x3010 DCDC_EM23CTRL0_TGL RW SYNC EM23 Control 0x3020 DCDC_PFMXCTRL_TGL RW SYNC PFMX Control Register 0x3028 DCDC_IF_TGL RWH INTFLAG Interrupt Flags 0x302C DCDC_IEN_TGL Interrupt Enable 0x3030 DCDC_STATUS_TGL Status Register...
Page 332: Dcdc_Ctrl - Control
Reference Manual EMU - Energy Management Unit 12.7.2 DCDC_CTRL - Control Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions IPKTMAXCTRL 0x10...
Page 333: Dcdc_Em01Ctrl0 - Em01 Control
Reference Manual EMU - Energy Management Unit 12.7.3 DCDC_EM01CTRL0 - EM01 Control Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 334: Dcdc_Em23Ctrl0 - Em23 Control
Reference Manual EMU - Energy Management Unit 12.7.4 DCDC_EM23CTRL0 - EM23 Control Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 335: Dcdc_Pfmxctrl - Pfmx Control Register
Reference Manual EMU - Energy Management Unit 12.7.5 DCDC_PFMXCTRL - PFMX Control Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 336: Dcdc_If - Interrupt Flags
Reference Manual EMU - Energy Management Unit 12.7.6 DCDC_IF - Interrupt Flags Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 337: Dcdc_Ien - Interrupt Enable
Reference Manual EMU - Energy Management Unit 12.7.7 DCDC_IEN - Interrupt Enable Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 338: Dcdc_Status - Status Register
Reference Manual EMU - Energy Management Unit 12.7.8 DCDC_STATUS - Status Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 339: Dcdc_Syncbusy - Syncbusy Status Register
Reference Manual EMU - Energy Management Unit 12.7.9 DCDC_SYNCBUSY - Syncbusy Status Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 340: Dcdc_Lock - Lock Register
Reference Manual EMU - Energy Management Unit 12.7.10 DCDC_LOCK - Lock Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 341: Prs - Peripheral Reflex System
Reference Manual PRS - Peripheral Reflex System 13. PRS - Peripheral Reflex System Quick Facts What? The PRS (Peripheral Reflex System) allows configu- rable, fast, and autonomous communication be- tween peripherals. Why? Events and signals from one peripheral can be used as input signals to trigger actions in other peripher- als.
Page 342: Functional Description
Reference Manual PRS - Peripheral Reflex System 13.3 Functional Description The PRS contains 12 asynchronous and 4 synchronous reflex channels. An overview of an asynchronous PRS reflex channel is shown Figure 13.1 PRS Asynchronous Channel Overview on page 342. Synchronous channels are similar but do not include the configura- ble logic block or SWLEVEL / SWPULSE features.
Page 343: Configurable Logic
Reference Manual PRS - Peripheral Reflex System 13.3.2 Configurable Logic The configurable logic feature enables a PRS channel to perform logic operations on the signal coming from the selected producer. Every asynchronous channel has a configurable logic block that can be programmed using the FNSEL field in the asynchronous chan- nel control register.
Page 344: Producers
Reference Manual PRS - Peripheral Reflex System FNSEL value Implemented Function (NOT A) OR B A OR (NOT B) A OR B The default value of FNSEL is 0xC, meaning that the input from the selected producer goes through unchanged. This feature can be used to combine multiple channels to get even more complex functions.
Page 345 Reference Manual PRS - Peripheral Reflex System 13.3.3.1 Producer Details Table 13.4. Synchronous PRS Producers Peripheral SOURCESEL Signal SIGSEL TIMER0 TIMER0 (0x01) TIMER1 TIMER1 (0x02) IADC0 IADC0 (0x03) SCANENTRYDONE SCANTABLEDONE SINGLEDONE TIMER2 TIMER2 (0x04) TIMER3 TIMER3 (0x05) TIMER4 TIMER4 (0x06) VDAC0 VDAC0 (0x07) CH0DONESYNC...
Page 346 Reference Manual PRS - Peripheral Reflex System Table 13.5. Asynchronous PRS Producers Peripheral SOURCESEL Signal SIGSEL IADC0 IADC0 (0x01) SCANENTRYDONE SCANTABLEDONE SINGLEDONE LETIMER0 LETIMER0 (0x02) BURTC BURTC (0x03) COMP OVERFLOW GPIO GPIO (0x04) PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 CMUL (0x05) CLKOUT0...
Page 347 Reference Manual PRS - Peripheral Reflex System Peripheral SOURCESEL Signal SIGSEL VDAC0 VDAC0L (0x0C) CH0WARM CH1WARM CH0DONEASYNC CH1DONEASYNC INTERNALTIMEROF REFRESHTIMEROF PCNT0 PCNT0 (0x0E) UFOF SYSRTC0 SYSRTC0 (0x0F) GRP0OUT0 GRP0OUT1 GRP1OUT0 GRP1OUT1 LESENSE LESENSE (0x10) DECOUT0 DECOUT1 DECOUT2 DECCMP HFXO0 HFXO0L (0x11) STATUS STATUS1 EUSART0...
Page 348 Reference Manual PRS - Peripheral Reflex System Peripheral SOURCESEL Signal SIGSEL TIMER1 TIMER1 (0x22) TIMER2 TIMER2 (0x23) TIMER3 TIMER3 (0x24) CORE CORE (0x25) CTIOUT0 CTIOUT1 CTIOUT2 CTIOUT3 AGCL (0x26) CCAREQ GAINADJUST GAINOK GAINREDUCED IFPKI1 IFPKQ2 IFPKRST AGC (0x27) PEAKDET PROPAGATED RSSIDONE BUFC BUFC (0x28)
Page 349 Reference Manual PRS - Peripheral Reflex System Peripheral SOURCESEL Signal SIGSEL MODEM MODEML (0x29) ADVANCE ANT0 ANT1 COHDSADET COHDSALIVE DCLK DOUT FRAMEDET MODEM (0x2A) FRAMESENT LOWCORR LRDSADET LRDSALIVE NEWSYMBOL NEWWND POSTPONE PREDET MODEMH (0x2B) PRESENT RSSIJUMP SYNCSENT TIMDET WEAK FRC (0x2C) DCLK DOUT silabs.com | Building a more connected world.
Page 350 Reference Manual PRS - Peripheral Reflex System Peripheral SOURCESEL Signal SIGSEL PROTIMER PROTIMERL (0x2D) LBTF LBTR PROTIMER (0x2E) LBTS T0MATCH T0UF T1MATCH T1UF SYNTH SYNTH (0x2F) MUX0 MUX1 RACL (0x30) ACTIVE LNAEN PAEN CTIOUT0 CTIOUT1 CTIOUT2 RAC (0x31) CTIOUT3 AUXADCDATA AUXADCDATAVALID TIMER4 TIMER4 (0x32)
Page 351: Consumers
Reference Manual PRS - Peripheral Reflex System Peripheral SOURCESEL Signal SIGSEL EUSART1 EUSART1L (0x33) IRDATX RXDATAV RXFL TXFL EUSART2 EUSART2L (0x35) IRDATX RXDATAV RXFL TXFL 13.3.4 Consumers Consumer peripherals can be set to listen to a PRS channel and perform an action based on the signal received on that channel. This is done by programming the PRSSEL or SPRSSEL in the consumer registers.
Page 352: Prs Register Map
Reference Manual PRS - Peripheral Reflex System 13.4 PRS Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 PRS_IPVERSION PRS IPVERSION 0x008 PRS_ASYNC_SWPULSE Software Pulse Register 0x00C PRS_ASYNC_SWLEVEL Software Level Register 0x010 PRS_ASYNC_PEEK Async Channel Values...
Page 353 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x0B0 PRS_CONSUMER_LETIM- START Consumer Register ER0_START 0x0B4 PRS_CONSUMER_LETIM- STOP Consumer Register ER0_STOP 0x0B8 PRS_CONSUMER_MO- MODEM DIN Consumer Register DEM_DIN 0x0BC PRS_CONSUM- S0IN Consumer Register ER_PCNT0_S0IN 0x0C0 PRS_CONSUM- S1IN Consumer Register ER_PCNT0_S1IN 0x0F0 PRS_CONSUMER_RAC_CLR...
Page 354 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x144 PRS_CONSUM- CTI1 Consumer Selection ER_CORE_CTIIN1 0x148 PRS_CONSUM- CTI2 Consumer Selection ER_CORE_CTIIN2 0x14C PRS_CONSUM- CTI3 Consumer Selection ER_CORE_CTIIN3 0x150 PRS_CONSUM- M33 Consumer Selection ER_CORE_M33RXEV 0x154 PRS_CONSUMER_TIM- CC0 Consumer Register ER0_CC0 0x158 PRS_CONSUMER_TIM-...
Page 355 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x1A4 PRS_CONSUMER_TIM- CC2 Consumer Register ER3_CC2 0x1A8 PRS_CONSUMER_TIMER3_DTI DTI Consumer Register 0x1AC PRS_CONSUMER_TIM- DTI Consumer Register ER3_DTIFS1 0x1B0 PRS_CONSUMER_TIM- DTI Consumer Register ER3_DTIFS2 0x1B4 PRS_CONSUMER_TIM- CC0 Consumer Register ER4_CC0 0x1B8 PRS_CONSUMER_TIM- CC1 Consumer Register...
Page 356 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x1014 PRS_SYNC_PEEK_SET Sync Channel Values 0x1018 PRS_ASYNC_CHx_CTRL_SET Async Channel Control Register 0x1048 PRS_SYNC_CHx_CTRL_SET Sync Channel Control Register 0x1058 PRS_CONSUM- CALDN Consumer Register ER_CMU_CALDN_SET 0x105C PRS_CONSUMER_CMU_CAL- CALUP Consumer Register UP_SET 0x1060 PRS_CONSUMER_EU- CLK Consumer Register...
Page 357 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x10C0 PRS_CONSUM- S1IN Consumer Register ER_PCNT0_S1IN_SET 0x10F0 PRS_CONSUM- CLR Consumer Register ER_RAC_CLR_SET 0x10F4 PRS_CONSUM- CTI Consumer Register ER_RAC_CTIIN0_SET 0x10F8 PRS_CONSUM- CTI Consumer Register ER_RAC_CTIIN1_SET 0x10FC PRS_CONSUM- CTI Consumer Register ER_RAC_CTIIN2_SET 0x1100 PRS_CONSUM-...
Page 358 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x1148 PRS_CONSUM- CTI2 Consumer Selection ER_CORE_CTIIN2_SET 0x114C PRS_CONSUM- CTI3 Consumer Selection ER_CORE_CTIIN3_SET 0x1150 PRS_CONSUM- M33 Consumer Selection ER_CORE_M33RXEV_SET 0x1154 PRS_CONSUMER_TIM- CC0 Consumer Register ER0_CC0_SET 0x1158 PRS_CONSUMER_TIM- CC1 Consumer Register ER0_CC1_SET 0x115C PRS_CONSUMER_TIM- CC2 Consumer Register...
Page 359 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x11A4 PRS_CONSUMER_TIM- CC2 Consumer Register ER3_CC2_SET 0x11A8 PRS_CONSUMER_TIM- DTI Consumer Register ER3_DTI_SET 0x11AC PRS_CONSUMER_TIM- DTI Consumer Register ER3_DTIFS1_SET 0x11B0 PRS_CONSUMER_TIM- DTI Consumer Register ER3_DTIFS2_SET 0x11B4 PRS_CONSUMER_TIM- CC0 Consumer Register ER4_CC0_SET 0x11B8 PRS_CONSUMER_TIM-...
Page 360 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x2000 PRS_IPVERSION_CLR PRS IPVERSION 0x2008 PRS_ASYNC_SWPULSE_CLR Software Pulse Register 0x200C PRS_ASYNC_SWLEVEL_CLR Software Level Register 0x2010 PRS_ASYNC_PEEK_CLR Async Channel Values 0x2014 PRS_SYNC_PEEK_CLR Sync Channel Values 0x2018 PRS_ASYNC_CHx_CTRL_CLR Async Channel Control Register 0x2048 PRS_SYNC_CHx_CTRL_CLR Sync Channel Control Register...
Page 361 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x20B4 PRS_CONSUMER_LETIM- STOP Consumer Register ER0_STOP_CLR 0x20B8 PRS_CONSUMER_MO- MODEM DIN Consumer Register DEM_DIN_CLR 0x20BC PRS_CONSUM- S0IN Consumer Register ER_PCNT0_S0IN_CLR 0x20C0 PRS_CONSUM- S1IN Consumer Register ER_PCNT0_S1IN_CLR 0x20F0 PRS_CONSUM- CLR Consumer Register ER_RAC_CLR_CLR 0x20F4 PRS_CONSUM-...
Page 362 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x213C PRS_CONSUM- TIMEOUT Consumer Register ER_HFXO0_TIMEOUT_CLR 0x2140 PRS_CONSUM- CTI0 Consumer Selection ER_CORE_CTIIN0_CLR 0x2144 PRS_CONSUM- CTI1 Consumer Selection ER_CORE_CTIIN1_CLR 0x2148 PRS_CONSUM- CTI2 Consumer Selection ER_CORE_CTIIN2_CLR 0x214C PRS_CONSUM- CTI3 Consumer Selection ER_CORE_CTIIN3_CLR 0x2150 PRS_CONSUM-...
Page 363 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x2198 PRS_CONSUMER_TIM- DTI Consumer Register ER2_DTIFS2_CLR 0x219C PRS_CONSUMER_TIM- CC0 Consumer Register ER3_CC0_CLR 0x21A0 PRS_CONSUMER_TIM- CC1 Consumer Register ER3_CC1_CLR 0x21A4 PRS_CONSUMER_TIM- CC2 Consumer Register ER3_CC2_CLR 0x21A8 PRS_CONSUMER_TIM- DTI Consumer Register ER3_DTI_CLR 0x21AC PRS_CONSUMER_TIM- DTI Consumer Register...
Page 364 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x21FC PRS_CONSUM- SRC1 Consumer Register ER_WDOG0_SRC1_CLR 0x2200 PRS_CONSUM- SRC0 Consumer Register ER_WDOG1_SRC0_CLR 0x2204 PRS_CONSUM- SRC1 Consumer Register ER_WDOG1_SRC1_CLR 0x3000 PRS_IPVERSION_TGL PRS IPVERSION 0x3008 PRS_ASYNC_SWPULSE_TGL Software Pulse Register 0x300C PRS_ASYNC_SWLEVEL_TGL Software Level Register 0x3010 PRS_ASYNC_PEEK_TGL...
Page 365 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x30A8 PRS_CONSUMER_LE- START Consumer Register SENSE_START_TGL 0x30AC PRS_CONSUMER_LETIM- CLEAR Consumer Register ER0_CLEAR_TGL 0x30B0 PRS_CONSUMER_LETIM- START Consumer Register ER0_START_TGL 0x30B4 PRS_CONSUMER_LETIM- STOP Consumer Register ER0_STOP_TGL 0x30B8 PRS_CONSUMER_MO- MODEM DIN Consumer Register DEM_DIN_TGL 0x30BC PRS_CONSUM- S0IN Consumer Register...
Page 366 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x3130 PRS_CONSUM- IN0 Consumer Register ER_SYSRTC0_IN0_TGL 0x3134 PRS_CONSUM- IN1 Consumer Register ER_SYSRTC0_IN1_TGL 0x3138 PRS_CONSUMER_HFXO0_OS- OSCREQ Consumer Register CREQ_TGL 0x313C PRS_CONSUM- TIMEOUT Consumer Register ER_HFXO0_TIMEOUT_TGL 0x3140 PRS_CONSUM- CTI0 Consumer Selection ER_CORE_CTIIN0_TGL 0x3144 PRS_CONSUM-...
Page 367 Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x318C PRS_CONSUMER_TIM- CC2 Consumer Register ER2_CC2_TGL 0x3190 PRS_CONSUMER_TIM- DTI Consumer Register ER2_DTI_TGL 0x3194 PRS_CONSUMER_TIM- DTI Consumer Register ER2_DTIFS1_TGL 0x3198 PRS_CONSUMER_TIM- DTI Consumer Register ER2_DTIFS2_TGL 0x319C PRS_CONSUMER_TIM- CC0 Consumer Register ER3_CC0_TGL 0x31A0 PRS_CONSUMER_TIM-...
Page 368: Prs Register Description
Reference Manual PRS - Peripheral Reflex System Offset Name Type Description 0x31F0 PRS_CONSUM- SYNCTRIG Consumer Register ER_VDAC0_SYN- CTRIGCH0_TGL 0x31F4 PRS_CONSUM- SYNCTRIG Consumer Register ER_VDAC0_SYN- CTRIGCH1_TGL 0x31F8 PRS_CONSUM- SRC0 Consumer Register ER_WDOG0_SRC0_TGL 0x31FC PRS_CONSUM- SRC1 Consumer Register ER_WDOG0_SRC1_TGL 0x3200 PRS_CONSUM- SRC0 Consumer Register ER_WDOG1_SRC0_TGL 0x3204 PRS_CONSUM-...
Page 369: Prs_Async_Swpulse - Software Pulse Register
Reference Manual PRS - Peripheral Reflex System 13.5.2 PRS_ASYNC_SWPULSE - Software Pulse Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 370: Prs_Async_Swlevel - Software Level Register
Reference Manual PRS - Peripheral Reflex System 13.5.3 PRS_ASYNC_SWLEVEL - Software Level Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 371: Prs_Async_Peek - Async Channel Values
Reference Manual PRS - Peripheral Reflex System 13.5.4 PRS_ASYNC_PEEK - Async Channel Values Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 372: Prs_Sync_Peek - Sync Channel Values
Reference Manual PRS - Peripheral Reflex System 13.5.5 PRS_SYNC_PEEK - Sync Channel Values Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 373: Prs_Async_Chx_Ctrl - Async Channel Control Register
Reference Manual PRS - Peripheral Reflex System 13.5.6 PRS_ASYNC_CHx_CTRL - Async Channel Control Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 374: Prs_Sync_Chx_Ctrl - Sync Channel Control Register
Reference Manual PRS - Peripheral Reflex System Name Reset Access Description Select input source for asynchronous PRS channel. See Asynchronous Producers table for details. Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 375: Prs_Consumer_Cmu_Caldn - Caldn Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.8 PRS_CONSUMER_CMU_CALDN - CALDN Consumer Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 376: Prs_Consumer_Eusart0_Clk - Clk Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.10 PRS_CONSUMER_EUSART0_CLK - CLK Consumer Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 377: Prs_Consumer_Eusart0_Trigger - Trigger Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.12 PRS_CONSUMER_EUSART0_TRIGGER - TRIGGER Consumer Register Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 378: Prs_Consumer_Eusart1_Rx - Rx Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.14 PRS_CONSUMER_EUSART1_RX - RX Consumer Register Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 379: Prs_Consumer_Eusart2_Clk - Clk Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.16 PRS_CONSUMER_EUSART2_CLK - CLK Consumer Register Offset Bit Position 0x078 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 380: Prs_Consumer_Eusart2_Trigger - Trigger Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.18 PRS_CONSUMER_EUSART2_TRIGGER - TRIGGER Consumer Register Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 381: Prs_Consumer_Iadc0_Singletrigger - Single Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.20 PRS_CONSUMER_IADC0_SINGLETRIGGER - SINGLE Consumer Register Offset Bit Position 0x08C Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 382: Prs_Consumer_Ldmaxbar_Dmareq1 - Dmareq1 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.22 PRS_CONSUMER_LDMAXBAR_DMAREQ1 - DMAREQ1 Consumer Register Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 383: Prs_Consumer_Letimer0_Clear - Clear Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.24 PRS_CONSUMER_LETIMER0_CLEAR - CLEAR Consumer Register Offset Bit Position 0x0AC Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 384: Prs_Consumer_Letimer0_Stop - Stop Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.26 PRS_CONSUMER_LETIMER0_STOP - STOP Consumer Register Offset Bit Position 0x0B4 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 385: Prs_Consumer_Pcnt0_S0In - S0In Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.28 PRS_CONSUMER_PCNT0_S0IN - S0IN Consumer Register Offset Bit Position 0x0BC Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 386: Prs_Consumer_Rac_Clr - Clr Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.30 PRS_CONSUMER_RAC_CLR - CLR Consumer Register Offset Bit Position 0x0F0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 387: Prs_Consumer_Rac_Ctiin1 - Cti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.32 PRS_CONSUMER_RAC_CTIIN1 - CTI Consumer Register Offset Bit Position 0x0F8 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 388: Prs_Consumer_Rac_Ctiin3 - Cti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.34 PRS_CONSUMER_RAC_CTIIN3 - CTI Consumer Register Offset Bit Position 0x100 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 389: Prs_Consumer_Rac_Rxdis - Rxdis Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.36 PRS_CONSUMER_RAC_RXDIS - RXDIS Consumer Register Offset Bit Position 0x108 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 390: Prs_Consumer_Rac_Txen - Txen Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.38 PRS_CONSUMER_RAC_TXEN - TXEN Consumer Register Offset Bit Position 0x110 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 391: Prs_Consumer_Setamper_Tampersrc26 - Tampersrc26 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.40 PRS_CONSUMER_SETAMPER_TAMPERSRC26 - TAMPERSRC26 Consumer Register Offset Bit Position 0x118 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 392: Prs_Consumer_Setamper_Tampersrc28 - Tampersrc28 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.42 PRS_CONSUMER_SETAMPER_TAMPERSRC28 - TAMPERSRC28 Consumer Register Offset Bit Position 0x120 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 393: Prs_Consumer_Setamper_Tampersrc30 - Tampersrc30 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.44 PRS_CONSUMER_SETAMPER_TAMPERSRC30 - TAMPERSRC30 Consumer Register Offset Bit Position 0x128 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 394: Prs_Consumer_Sysrtc0_In0 - In0 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.46 PRS_CONSUMER_SYSRTC0_IN0 - IN0 Consumer Register Offset Bit Position 0x130 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 395: Prs_Consumer_Hfxo0_Oscreq - Oscreq Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.48 PRS_CONSUMER_HFXO0_OSCREQ - OSCREQ Consumer Register Offset Bit Position 0x138 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 396: Prs_Consumer_Core_Ctiin0 - Cti0 Consumer Selection
Reference Manual PRS - Peripheral Reflex System 13.5.50 PRS_CONSUMER_CORE_CTIIN0 - CTI0 Consumer Selection Offset Bit Position 0x140 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 397: Prs_Consumer_Core_Ctiin2 - Cti2 Consumer Selection
Reference Manual PRS - Peripheral Reflex System 13.5.52 PRS_CONSUMER_CORE_CTIIN2 - CTI2 Consumer Selection Offset Bit Position 0x148 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 398: Prs_Consumer_Core_M33Rxev - M33 Consumer Selection
Reference Manual PRS - Peripheral Reflex System 13.5.54 PRS_CONSUMER_CORE_M33RXEV - M33 Consumer Selection Offset Bit Position 0x150 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 399: Prs_Consumer_Timer0_Cc1 - Cc1 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.56 PRS_CONSUMER_TIMER0_CC1 - CC1 Consumer Register Offset Bit Position 0x158 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 400: Prs_Consumer_Timer0_Dti - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.58 PRS_CONSUMER_TIMER0_DTI - DTI Consumer Register Offset Bit Position 0x160 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 401: Prs_Consumer_Timer0_Dtifs2 - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.60 PRS_CONSUMER_TIMER0_DTIFS2 - DTI Consumer Register Offset Bit Position 0x168 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 402: Prs_Consumer_Timer1_Cc1 - Cc1 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.62 PRS_CONSUMER_TIMER1_CC1 - CC1 Consumer Register Offset Bit Position 0x170 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 403: Prs_Consumer_Timer1_Dti - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.64 PRS_CONSUMER_TIMER1_DTI - DTI Consumer Register Offset Bit Position 0x178 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 404: Prs_Consumer_Timer1_Dtifs2 - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.66 PRS_CONSUMER_TIMER1_DTIFS2 - DTI Consumer Register Offset Bit Position 0x180 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 405: Prs_Consumer_Timer2_Cc1 - Cc1 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.68 PRS_CONSUMER_TIMER2_CC1 - CC1 Consumer Register Offset Bit Position 0x188 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 406: Prs_Consumer_Timer2_Dti - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.70 PRS_CONSUMER_TIMER2_DTI - DTI Consumer Register Offset Bit Position 0x190 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 407: Prs_Consumer_Timer2_Dtifs2 - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.72 PRS_CONSUMER_TIMER2_DTIFS2 - DTI Consumer Register Offset Bit Position 0x198 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 408: Prs_Consumer_Timer3_Cc1 - Cc1 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.74 PRS_CONSUMER_TIMER3_CC1 - CC1 Consumer Register Offset Bit Position 0x1A0 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 409: Prs_Consumer_Timer3_Dti - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.76 PRS_CONSUMER_TIMER3_DTI - DTI Consumer Register Offset Bit Position 0x1A8 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 410: Prs_Consumer_Timer3_Dtifs2 - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.78 PRS_CONSUMER_TIMER3_DTIFS2 - DTI Consumer Register Offset Bit Position 0x1B0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 411: Prs_Consumer_Timer4_Cc1 - Cc1 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.80 PRS_CONSUMER_TIMER4_CC1 - CC1 Consumer Register Offset Bit Position 0x1B8 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 412: Prs_Consumer_Timer4_Dti - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.82 PRS_CONSUMER_TIMER4_DTI - DTI Consumer Register Offset Bit Position 0x1C0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 413: Prs_Consumer_Timer4_Dtifs2 - Dti Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.84 PRS_CONSUMER_TIMER4_DTIFS2 - DTI Consumer Register Offset Bit Position 0x1C8 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 414: Prs_Consumer_Usart0_Ir - Ir Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.86 PRS_CONSUMER_USART0_IR - IR Consumer Register Offset Bit Position 0x1D0 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 415: Prs_Consumer_Usart0_Trigger - Trigger Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.88 PRS_CONSUMER_USART0_TRIGGER - TRIGGER Consumer Register Offset Bit Position 0x1D8 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 416: Prs_Consumer_Vdac0_Asynctrigch1 - Asynctrig Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.90 PRS_CONSUMER_VDAC0_ASYNCTRIGCH1 - ASYNCTRIG Consumer Register Offset Bit Position 0x1EC Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 417: Prs_Consumer_Vdac0_Synctrigch1 - Synctrig Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.92 PRS_CONSUMER_VDAC0_SYNCTRIGCH1 - SYNCTRIG Consumer Register Offset Bit Position 0x1F4 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 418: Prs_Consumer_Wdog0_Src1 - Src1 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.94 PRS_CONSUMER_WDOG0_SRC1 - SRC1 Consumer Register Offset Bit Position 0x1FC Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 419: Prs_Consumer_Wdog1_Src1 - Src1 Consumer Register
Reference Manual PRS - Peripheral Reflex System 13.5.96 PRS_CONSUMER_WDOG1_SRC1 - SRC1 Consumer Register Offset Bit Position 0x204 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 420: Gpcrc - General Purpose Cyclic Redundancy Check
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14. GPCRC - General Purpose Cyclic Redundancy Check Quick Facts What? The GPCRC is an error-detecting module commonly used in digital networks and storage systems to de- tect accidental changes to data. Why? The GPCRC module can detect errors in data, giv- ing a higher system reliability and robustness.
Page 421: Functional Description
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.3 Functional Description An overview of the GPCRC module is shown in Figure 14.1 GPCRC Overview on page 421. GPCRC Module DATAREV bit reversal DATA byte reversal DATABYTEREV INPUTDATA byte byte-level reorder Hardware CRC reversal...
Page 422: Polynomial Specification
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.3.1 Polynomial Specification POLYSEL in GPCRC_CTRL selects between 32-bit and 16-bit polynomial functions. When a 32-bit polynomial is selected, the fixed IEEE 802.3 polynomial(0x04C11DB7) is used. When a 16-bit polynomial is selected, any valid polynomial can be defined by the user in GPCRC_POLY.
Page 423: Byte-Level Bit Reversal And Byte Reordering
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.3.5 Byte-Level Bit Reversal and Byte Reordering The byte-level bit reversal and byte reordering operations occur before the data is used in the CRC calculation. Byte reordering can occur on words or half words. The hardware ignores the BYTEREVERSE field with any byte writes or operations with byte mode ena- bled (BYTEMODE = 1), but the bit reversal settings (BITREVERSE) are still applied to the byte.
Page 424 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Byte 3 Byte 2 Byte 1 Byte 0 Input data is big endian, MSB-first BYTEREVERSE = 1 8'h00 8'h00 Byte 0 Byte 1 BITREVERSE = 1 8'h00 8'h00 Byte 0 Byte 1 Data is now 16-bit little endian, LSB-first for CRC calculation...
Page 425 Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Input Width(bits) BYTEREVERSE Setting BITREVERSE Setting Input to CRC Calculation Notes: 1. X indicates a "don't care". 2. Bn is the byte field within the word. 3. 'Bn is the bit-reversed byte field within the word. silabs.com | Building a more connected world.
Page 426: Gpcrc Register Map
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.4 GPCRC Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPCRC_IPVERSION IP Version ID 0x004 GPCRC_EN CRC Enable 0x008 GPCRC_CTRL Control Register 0x00C GPCRC_CMD Command Register...
Page 427: Gpcrc Register Description
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Offset Name Type Description 0x2024 GPCRC_DATA_CLR RH(r) CRC Data Register 0x2028 GPCRC_DATAREV_CLR RH(r) CRC Data Reverse Register 0x202C GPCRC_DATABYTEREV_CLR RH(r) CRC Data Byte Reverse Register 0x3000 GPCRC_IPVERSION_TGL IP Version ID 0x3004 GPCRC_EN_TGL CRC Enable 0x3008...
Page 428: Gpcrc_En - Crc Enable
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.2 GPCRC_EN - CRC Enable Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 429: Gpcrc_Ctrl - Control Register
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.3 GPCRC_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 430: Gpcrc_Cmd - Command Register
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 14.5.4 GPCRC_CMD - Command Register Offset Bit Position 0x00C...
Page 431: Gpcrc_Poly - Crc Polynomial Value
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.6 GPCRC_POLY - CRC Polynomial Value Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 432: Gpcrc_Inputdatahword - Input 16-Bit Data Register
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.8 GPCRC_INPUTDATAHWORD - Input 16-Bit Data Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 433: Gpcrc_Data - Crc Data Register
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.10 GPCRC_DATA - CRC Data Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:0 DATA R(r) CRC Data Register CRC Data Register, read only. The CRC data register may still be indirectly written from software, by writing the INIT register and then issue an INITIALIZE command.
Page 434: Gpcrc_Databyterev - Crc Data Byte Reverse Register
Reference Manual GPCRC - General Purpose Cyclic Redundancy Check 14.5.12 GPCRC_DATABYTEREV - CRC Data Byte Reverse Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:0 DATABYTEREV R(r) Data Byte Reverse Value Byte reversed version of CRC Data register. When a 32-bit CRC polynomial is selected, the bytes are swizzled to {B0, B1, B2, B3}.
Page 435: Sysrtc - System Rtc
Reference Manual SYSRTC - System RTC 15. SYSRTC - System RTC Quick Facts What? The System Real-Time Counter (SYSRTC) is a 32- bit Real Time Clock ensuring timekeeping in low en- ergy modes. Why? Timekeeping over long time periods while using as little power as possible is required in many low pow- er applications.
Page 436: Features
Reference Manual SYSRTC - System RTC 15.2 Features • 32-bit counter • Debug mode • 32.768 kHz LFXO or LFRCO / 1 kHz ULFRCO • Low energy wake-up source • Separate groups of capture / compare registers and signals • MCU core and Radio core each control one group •...
Page 437: Capture Events
Reference Manual SYSRTC - System RTC 15.3.4 Capture Events SYSRTC groups support counter value capture triggered by PRS consumer signals. For group "n" the SYSRTC0 "INn" PRS consumer is used to trigger captures. Capture can be triggered on RISING, FALLING, or BOTH edges, according to the setting programmed in CAP0EDGE of the GRPn_CTRL register.
Page 438: Sysrtc Register Map
Reference Manual SYSRTC - System RTC 15.4 SYSRTC Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 SYSRTC_IPVERSION IP VERSION 0x004 SYSRTC_EN RW ENABLE Module Enable Register 0x008 SYSRTC_SWRST RW SWRST Software Reset Register 0x00C SYSRTC_CFG...
Page 439 Reference Manual SYSRTC - System RTC Offset Name Type Description 0x2004 SYSRTC_EN_CLR RW ENABLE Module Enable Register 0x2008 SYSRTC_SWRST_CLR RW SWRST Software Reset Register 0x200C SYSRTC_CFG_CLR RW CONFIG Configuration Register 0x2010 SYSRTC_CMD_CLR W LFSYNC Command Register 0x2014 SYSRTC_STATUS_CLR Status Register 0x2018 SYSRTC_CNT_CLR RWH LFSYNC...
Page 440: Sysrtc Register Description
Reference Manual SYSRTC - System RTC 15.5 SYSRTC Register Description 15.5.1 SYSRTC_IPVERSION - IP VERSION Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP VERSION Gives access to the IP VERSION of SYSRTC 15.5.2 SYSRTC_EN - Module Enable Register Offset Bit Position 0x004...
Page 441: Sysrtc_Swrst - Software Reset Register
Reference Manual SYSRTC - System RTC 15.5.3 SYSRTC_SWRST - Software Reset Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 442: Sysrtc_Cmd - Command Register
Reference Manual SYSRTC - System RTC 15.5.5 SYSRTC_CMD - Command Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions STOP W(nB)
Page 443: Sysrtc_Cnt - Counter Value Register
Reference Manual SYSRTC - System RTC 15.5.7 SYSRTC_CNT - Counter Value Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:0 Counter Value Gives access to the counter value of the SYSRTC. 15.5.8 SYSRTC_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x01C...
Page 444: Sysrtc_Lock - Configuration Lock Register
Reference Manual SYSRTC - System RTC 15.5.9 SYSRTC_LOCK - Configuration Lock Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 445: Sysrtc_Grp0_Ien - Group Interrupt Enables
Reference Manual SYSRTC - System RTC 15.5.11 SYSRTC_GRP0_IEN - Group Interrupt Enables Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 446: Sysrtc_Grp0_Ctrl - Group Control Register
Reference Manual SYSRTC - System RTC 15.5.12 SYSRTC_GRP0_CTRL - Group Control Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 447: Sysrtc_Grp0_Cmp0Value - Compare 0 Value Register
Reference Manual SYSRTC - System RTC Name Reset Access Description CMP1EN Compare 1 Enable Set this bit to enable Compare 1 CMP0EN Compare 0 Enable Set this bit to enable Compare 0 15.5.13 SYSRTC_GRP0_CMP0VALUE - Compare 0 Value Register Offset Bit Position 0x04C Reset...
Page 448: Sysrtc_Grp0_Cap0Value - Capture 0 Value Register
Reference Manual SYSRTC - System RTC 15.5.15 SYSRTC_GRP0_CAP0VALUE - Capture 0 Value Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:0 CAP0VALUE Capture 0 Value Capture 0 captured value 15.5.16 SYSRTC_GRP0_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x058 Reset...
Page 449: Burtc - Back-Up Real Time Counter
Reference Manual BURTC - Back-Up Real Time Counter 16. BURTC - Back-Up Real Time Counter Quick Facts What? The BURTC is a 32 bit counter which operates on a low frequency oscillator, and is capable of running in all Energy Modes. Why? It can provide periodic Wakeup events and PRS sig- nals which can be used to wake up peripherals from...
Page 450: Functional Description
Reference Manual BURTC - Back-Up Real Time Counter 16.3 Functional Description An overview of the BURTC module is shown in Figure 16.1 BURTC Overview on page 450. 0xFFFFFFFF BURTC_COMP BURTC_CFG.CNTPRESC Clear BURTC_CFG.COMPTOP Counter Pre-Counter BURTCCLK BURTC_CNT BURTC_PRECNT [31:0] BURTC_COMP COMP PRS output 0xFFFFFFFF Compare...
Page 451: Counter
Reference Manual BURTC - Back-Up Real Time Counter 16.3.4 Counter The BURTC consists of two counters: the 32-bit main counter, BURTC_CNT, and a 15-bit pre-counter, BURTC_PRECNT. The pre- counter is a free running counter clocked by low frequency clock, used to generate a specific frequency for the main counter. The pre- counter will be counting only when the BURTC_CFG.CNTPRESC value is set greater than 0.
Page 452: Compare Channel
Reference Manual BURTC - Back-Up Real Time Counter 16.3.5 Compare Channel A single compare channel is available in the BURTC. The compare value is set in BURTC_COMP register. If BURTC_CFG.COMPTOP is set, the main counter will clear to 0 when it matches the value set in BURTC_COMP. 16.3.6 Interrupts The BURTC has 2 interrupts: one for Overflow and another for for Compare match event.
Page 453: Burtc Register Map
Reference Manual BURTC - Back-Up Real Time Counter 16.4 BURTC Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 BURTC_IPVERSION IP Version ID 0x004 BURTC_EN RW ENABLE Module Enable Register 0x008 BURTC_CFG RW CONFIG Configuration Register...
Page 454: Burtc Register Description
Reference Manual BURTC - Back-Up Real Time Counter Offset Name Type Description 0x2024 BURTC_EM4WUEN_CLR EM4 Wakeup Request Enable Register 0x2028 BURTC_SYNCBUSY_CLR Synchronization Busy Register 0x202C BURTC_LOCK_CLR Configuration Lock Register 0x2030 BURTC_COMP_CLR RW LFSYNC Compare Value Register 0x3000 BURTC_IPVERSION_TGL IP Version ID 0x3004 BURTC_EN_TGL RW ENABLE...
Page 455: Burtc_En - Module Enable Register
Reference Manual BURTC - Back-Up Real Time Counter 16.5.2 BURTC_EN - Module Enable Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 456: Burtc_Cfg - Configuration Register
Reference Manual BURTC - Back-Up Real Time Counter 16.5.3 BURTC_CFG - Configuration Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 457: Burtc_Cmd - Command Register
Reference Manual BURTC - Back-Up Real Time Counter Name Reset Access Description ENABLE The top value of the BURTC is given by COMP DEBUGRUN Debug Mode Run Enable Set this bit to enable the BURTC to keep running in debug Value Mode Description...
Page 458: Burtc_Status - Status Register
Reference Manual BURTC - Back-Up Real Time Counter 16.5.5 BURTC_STATUS - Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 459: Burtc_Ien - Interrupt Enable Register
Reference Manual BURTC - Back-Up Real Time Counter 16.5.7 BURTC_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 460: Burtc_Cnt - Counter Value Register
Reference Manual BURTC - Back-Up Real Time Counter 16.5.9 BURTC_CNT - Counter Value Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:0 Counter Value Gives access to the counter value of the BURTC. 16.5.10 BURTC_EM4WUEN - EM4 Wakeup Request Enable Register Offset Bit Position 0x024...
Page 461: Burtc_Syncbusy - Synchronization Busy Register
Reference Manual BURTC - Back-Up Real Time Counter 16.5.11 BURTC_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 462: Burtc_Lock - Configuration Lock Register
Reference Manual BURTC - Back-Up Real Time Counter 16.5.12 BURTC_LOCK - Configuration Lock Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 463: Buram - Backup Ram
Reference Manual BURAM - Backup RAM 17. BURAM - Backup RAM Quick Facts What? The BURAM is a dedicated 128-byte low-power RAM that is retained in EM4. Why? Most of the system, including the RAM, is powered off at EM4 entry to minimize current draw. The pur- pose of the BURAM is to retain critical data for use when the system wakes up.
Page 464: Buram Register Description
Reference Manual BURAM - Backup RAM 17.4 BURAM Register Description 17.4.1 BURAM_RETx_REG - Retention Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 RETREG RW(nB) Latch based Retention register The RETREG registers are undefined out of reset. Any written RETREG values will be retained through any event other than a brownout or power-on reset.
Page 465: Letimer - Low Energy Timer
Reference Manual LETIMER - Low Energy Timer 18. LETIMER - Low Energy Timer Quick Facts What? The LETIMER is a down-counter that can keep track of time and output configurable waveforms. Running on a 32768 Hz clock, the LETIMER is available in LETIMER EM0 Active, EM1 Sleep, EM2 DeepSleep, and EM3 Stop.
Page 466: Functional Description
Reference Manual LETIMER - Low Energy Timer 18.3 Functional Description An overview of the LETIMER module is shown in Figure 18.1 LETIMER Overview on page 466. The LETIMER is a 24-bit down-counter with two compare registers, LETIMERn_COMP0 and LETIMERn_COMP1. The LETIMERn_TOP register can optionally act as a top value for the counter.
Page 467: Internal Overview
Reference Manual LETIMER - Low Energy Timer 18.3.1 Internal Overview Timer The timer value can be read using the LETIMERn_CNT register. The value can be written, and it can also be cleared by setting the CLEAR command bit in LETIMERn_CMD. If the CLEAR and START commands are issued at the same time, the timer will be cleared, then start counting at the top value.
Page 468 Reference Manual LETIMER - Low Energy Timer 18.3.2 Free Running Mode In free-running mode, the LETIMER acts as a regular timer and the repeat operation is disabled. When started, the timer runs until it is stopped using the STOP command bit in LETIMERn_CMD/PRS. A state machine for this mode is shown in Figure 18.2 LETIMER State Machine for Free-running Mode on page 468 Wait for positive clock edge...
Page 469: One-Shot Mode
Reference Manual LETIMER - Low Energy Timer 18.3.3 One-shot Mode The one-shot repeat mode is the most basic repeat mode. In this mode, the repeat register LETIMERn_REP0 is decremented every time the timer underflows, and the timer stops when LETIMERn_REP0 goes from 1 to 0. In this mode, the timer counts down LETI- MERn_REP0 times, i.e.
Page 470: Buffered Mode
Reference Manual LETIMER - Low Energy Timer 18.3.4 Buffered Mode The Buffered repeat mode allows buffered timer operation. When started, the timer runs LETIMERn_REP0 number of times. If LETI- MERn_REP1 has been written since the last time it was used and if it is nonzero, LETIMERn_REP1 is then loaded into LETI- MERn_REP0, and counting continues the new number of times.
Page 471: Double Mode
Reference Manual LETIMER - Low Energy Timer 18.3.5 Double Mode The Double repeat mode works much like the one-shot repeat mode. The difference is that, where the one-shot mode counts as long as LETIMERn_REP0 is larger than 0, the double mode counts as long as either LETIMERn_REP0 or LETIMERn_REP1 is larger than 0.
Page 472: Clock Frequency
Reference Manual LETIMER - Low Energy Timer 18.4 Clock Frequency The LETIMER clock source (EM23GRPACLK) is selected in the Clock Management Unit (CMU), and is typically configured to have a frequency of 32 kHz in EM0/1/2 and 1 kHz in EM3. The LETIMER clock prescaler is defined by LETIMERn_CTRL->CNTPRESC. The LETIMER Prescaled clock frequency is given by Figure 18.6 LETIMER Clock Frequency on page 472.
Page 473: Prs Input Triggers
Reference Manual LETIMER - Low Energy Timer 18.5 PRS Input Triggers The LETIMER can be configured to start, stop, and/or clear based on PRS inputs. The diagram showing the functions of the PRS input triggers is shown in Figure 18.7 LETIMER PRS input triggers. on page 473.
Page 474: Output Action
Reference Manual LETIMER - Low Energy Timer 18.7 Output Action For each of the Outputs, an output action can be set. The output actions can be set by configuring UFOA0 and UFOA1 in LETIMERn_CTRL. UFOA0 defines the action on output 0, while UFOA1 defines the action on output 1.
Page 475: Programmer's Model
Reference Manual LETIMER - Low Energy Timer 18.12 Programmer's Model Important Note : Before writing any LFSYNC register, the module must be enabled ( LETIMER_EN->EN) and the LETIMER_SYN- CBUSY register should be polled to ensure the SYNC busy of that particular register field is not high. Write LETIMER Configuration into LETIMER_CTRL Register Enable clock to LETIMER module by setting LETIMER_EN->EN = 1 If used, write compare values into LETIMER_COMP0 and LETIMER_COMP1...
Page 476: One Shot Mode
Reference Manual LETIMER - Low Energy Timer 18.12.2 One Shot Mode LETIMER operation in ONESHOT Mode with different output modes are shown in Figure 18.9 LETIMER - One Shot Mode Waveform on page 476. In this example, REPMODE in LETIMERn_CTRL is set to ONESHOT, CNTTOPEN also in LETIMERn_CTRL has been set and LETIMERn_TOP has been written to 3 and LETIMERn_REP0 has been written to 3.
Page 477: Buffered Mode
Reference Manual LETIMER - Low Energy Timer 18.12.4 BUFFERED Mode In BUFFERED Mode LETIMERn_TOPBUFF and LETIMERn_REP1 registers are used as Buffers for LETIMERn_TOP and LETI- MERn_REP0 respectiverly. If both LETIMERn_TOP and LETIMERn_REP0 are 0 in buffered mode, and CNTTOPEN and BUFTOP in LETIMERn_CTRL are set, the values of LETIMERn_TOPBUFF and LETIMERn_REP1 are loaded into LETIMERn_TOP and LETI- MERn_REP0 respectively when the timer is started.
Page 478: Continuous Output Generation
Reference Manual LETIMER - Low Energy Timer 18.12.5 Continuous Output Generation In some scenarios, it might be desired to make LETIMER generate a continuous waveform. Very simple constant waveforms can be generated without the repeat counter as shown in Figure 18.8 LETIMER - Free Running Mode Waveform on page 475, but to generate changing waveforms, using the repeat counter and buffer registers can prove advantageous.
Page 479: Pwm Output
Reference Manual LETIMER - Low Energy Timer Note: Multiple LETIMER cycles are required to write a value to the LETIMER registers. The example in Figure 18.12 LETIMER - Con- tinuous Operation on page 478 assumes that writes are done in advance so they arrive in the LETIMER as described in the figure. Figure 18.13 LETIMERn_CNT Not Initialized to 0 on page 479 shows an example where the LETIMER is started while LETI- MERn_CNT is nonzero.
Page 480: Letimer Register Map
Reference Manual LETIMER - Low Energy Timer 18.13 LETIMER Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 LETIMER_IPVERSION IP Version 0x004 LETIMER_EN RW ENABLE Module En 0x008 LETIMER_SWRST RW SWRST Software Reset Register 0x00C LETIMER_CTRL...
Page 481 Reference Manual LETIMER - Low Energy Timer Offset Name Type Description 0x1050 LETIMER_PRSMODE_SET PRS Input Mode Select Register 0x2000 LETIMER_IPVERSION_CLR IP Version 0x2004 LETIMER_EN_CLR RW ENABLE Module En 0x2008 LETIMER_SWRST_CLR RW SWRST Software Reset Register 0x200C LETIMER_CTRL_CLR Control Register 0x2010 LETIMER_CMD_CLR W LFSYNC Command Register...
Page 482: Letimer Register Description
Reference Manual LETIMER - Low Energy Timer 18.14 LETIMER Register Description 18.14.1 LETIMER_IPVERSION - IP Version Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 483: Letimer_Swrst - Software Reset Register
Reference Manual LETIMER - Low Energy Timer 18.14.3 LETIMER_SWRST - Software Reset Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 484: Letimer_Ctrl - Control Register
Reference Manual LETIMER - Low Energy Timer 18.14.4 LETIMER_CTRL - Control Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 485 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description ENABLE The top value of the LETIMER is given by COMP0 BUFTOP Buffered Top Set to load TOPBUFF into TOP when REP0 reaches 0 in BUFFERED mode, allowing a buffered top value. Value Mode Description...
Page 486: Letimer_Cmd - Command Register
Reference Manual LETIMER - Low Energy Timer Name Reset Access Description BUFFERED The counter counts REP0 times. If REP1 has been written, it is loaded into REP0 when REP0 reaches zero, otherwise the counter stops DOUBLE Both REP0 and REP1 are decremented when the LETIMER wraps around.
Page 487: Letimer_Status - Status Register
Reference Manual LETIMER - Low Energy Timer 18.14.6 LETIMER_STATUS - Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 488: Letimer_Comp0 - Compare Value Register
Reference Manual LETIMER - Low Energy Timer 18.14.8 LETIMER_COMP0 - Compare Value Register 0 Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 489: Letimer_Top - Counter Top Value Register
Reference Manual LETIMER - Low Energy Timer 18.14.10 LETIMER_TOP - Counter TOP Value Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 490: Letimer_Rep0 - Repeat Counter Register 0
Reference Manual LETIMER - Low Energy Timer 18.14.12 LETIMER_REP0 - Repeat Counter Register 0 Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 491: Letimer_If - Interrupt Flag Register
Reference Manual LETIMER - Low Energy Timer 18.14.14 LETIMER_IF - Interrupt Flag Register Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 492: Letimer_Ien - Interrupt Enable Register
Reference Manual LETIMER - Low Energy Timer 18.14.15 LETIMER_IEN - Interrupt Enable Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 493: Letimer_Lock - Configuration Lock Register
Reference Manual LETIMER - Low Energy Timer 18.14.16 LETIMER_LOCK - Configuration Lock Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 494: Letimer_Syncbusy - Synchronization Busy Register
Reference Manual LETIMER - Low Energy Timer 18.14.17 LETIMER_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 495: Letimer_Prsmode - Prs Input Mode Select Register
Reference Manual LETIMER - Low Energy Timer 18.14.18 LETIMER_PRSMODE - PRS Input Mode Select Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 496 Reference Manual LETIMER - Low Energy Timer Name Reset Access Description FALLING Falling edge of selected PRS input can start the LETIMER BOTH Both the rising or falling edge of the selected PRS input can start the LETIMER 17:0 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 497: Timer - Timer/Counter
Reference Manual TIMER - Timer/Counter 19. TIMER - Timer/Counter Quick Facts What? The TIMER (Timer/Counter) keeps track of timing and counts events, generates output waveforms, and triggers timed actions in other peripherals. Why? Most applications have activities that need to be USART timed accurately with as little CPU intervention and energy consumption as possible.
Page 498: Features
Reference Manual TIMER - Timer/Counter 19.2 Features • 16/32-bit auto reload up/down counter • Dedicated 16/32-bit reload register which serves as counter maximum • 3 or 4 Compare/Capture channels • Individually configurable as either input capture or output compare/PWM • Multiple Counter modes •...
Page 499: Functional Description
Reference Manual TIMER - Timer/Counter • Dead-Time Insertion Unit • Complementary PWM outputs with programmable dead-time • Dead-time is specified independently for rising and falling edge • 10-bit prescaler • 6-bit time value • Outputs have configurable polarity • Outputs can be set inactive individually by software. •...
Page 500: Counter Modes
Reference Manual TIMER - Timer/Counter 19.3.2 Counter Modes The timer consists of a counter that can be configured to the following modes, using the MODE field in TIMERn_CFG: • Up-count: Counter counts up until it reaches the value in TIMERn_TOP, where it is reset to 0 before counting up again. •...
Page 501 Reference Manual TIMER - Timer/Counter 19.3.2.2 Operation Figure 19.2 TIMER Hardware Timer/Counter Control on page 501 shows the hardware timer/counter control. Software can start or stop the counter by setting the START or STOP bits in TIMERn_CMD. The counter value (CNT in TIMERn_CNT) can always be written by software to any 16/32-bit value.
Page 502 Reference Manual TIMER - Timer/Counter 19.3.2.4 Peripheral Clock The peripheral clock for the timer (HFPERCLK ) clocks the logic for the timer block, even when it is not the selected clock source. TIMERn All TIMER instances in this device family use EM01GRPACLK selected in CMU_EM01GRPACLKCTRL_CLKSEL as their peripheral clock source (HFPERCLK TIMERn The peripheral clock to each timer can be used as a source with a configurable 10-bit prescaler.
Page 503 Reference Manual TIMER - Timer/Counter 19.3.2.8 Top Value Buffer The TIMERn_TOP register can be altered either by writing it directly or by writing to the TIMER_TOPB (buffer) register. When writing to the buffer register the TIMERn_TOPB register will be written to TIMERn_TOP on the next update event. Buffering ensures that the TOP value is not set below the actual count value.
Page 504 Reference Manual TIMER - Timer/Counter 19.3.2.9 Quadrature Decoder Quadrature decoding mode is used to track motion and determine both rotation direction and position. The quadrature decoder uses two input channels that are 90 degrees out of phase (see Figure 19.6 TIMER Quadrature Encoded Inputs on page 504).
Page 505 Reference Manual TIMER - Timer/Counter The quadrature decoder can be set in either X2 or X4 mode, which is configured in the QDM bit in TIMERn_CFG. See Figure 19.7 TIMER Quadrature Decoder Configuration on page 504 19.3.2.10 X2 Decoding Mode In X2 Decoding mode, the counter increments or decrements on every edge of Channel A, see Table 19.1 TIMER Counter Response in X2 Decoding Mode on page 505...
Page 506: Compare/Capture Channels
Reference Manual TIMER - Timer/Counter 19.3.2.12 Rotational Position To calculate a position Figure 19.10 TIMER Rotational Position Equation on page 506 can be used. pos° = (CNT/X x N) x 360° Figure 19.10. TIMER Rotational Position Equation where X = Encoding type and N = Number of pulses per revolution. 19.3.3 Compare/Capture Channels The timer contains compare/capture channels, which can be independently configured in the following modes: 1.
Page 507 Reference Manual TIMER - Timer/Counter 19.3.3.3 Input Capture In input capture, the counter value (TIMERn_CNT) can be captured in the Input Capture Register (TIMERn_CCx_ICF) (see Figure 19.12 TIMER Input Capture on page 507). The CCPOL bits in TIMERn_STATUS indicate the polarity of the edge that triggered the capture in TIMERn_CCx_ICF.
Page 508 Reference Manual TIMER - Timer/Counter 19.3.3.4 Period/Pulse-Width Capture Period and/or pulse-width capture can only be possible with Channel 0 (CC0), because this is the only channel that can start and stop the timer. This can be done by setting the RISEA field in TIMERn_CTRL to Clear&Start, and selecting the desired input from either external pin or PRS, see Figure 19.13 TIMER Period and/or Pulse Width Capture on page 508.
Page 509 Reference Manual TIMER - Timer/Counter 19.3.3.5 Compare Each compare/capture channel contains a comparator which outputs a compare match if the contents of TIMERn_CCx_OC matches the counter value, see Figure 19.14 TIMER Block Diagram Showing Comparison Functionality on page 509. In compare mode, each compare channel can be configured to either set, clear or toggle the output on an event (compare match, overflow or underflow).
Page 510 Reference Manual TIMER - Timer/Counter COIST OUTINV Output Compare/ PWM x TIMERN.CCx Figure 19.15. TIMER Output Logic 19.3.3.6 Compare Mode Registers When running in output compare or PWM mode, the value in TIMERn_CCx_OC will be compared against the count value. In Compare mode the output can be configured to toggle, clear or set on compare match, overflow, and underflow through the CMOA, COFOA and CUFOA fields in TIMERn_CCx_CTRL.
Page 511 Reference Manual TIMER - Timer/Counter 19.3.3.7 Frequency Generation (FRG) Frequency generation (see Figure 19.17 TIMER Up-count Frequency Generation on page 511) can be achieved in compare mode by: • Setting the counter in up-count mode • Enabling buffering of the TOP value. •...
Page 512 Reference Manual TIMER - Timer/Counter 19.3.3.9 Up-count (Single-slope) PWM If the counter is set to up-count and the compare/capture channel is put in PWM mode, single slope PWM output will be generated (see Figure 19.20 TIMER Up-count PWM Generation on page 512).
Page 513 Reference Manual TIMER - Timer/Counter 19.3.3.10 2x Count Mode (Up-count) When the timer is set in 2x mode, the TIMER will count up by two for every (prescaled) clock. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd OC value will generate a match on the closest lower even value as shown in Figure 19.25 TIMER CC Out in 2x Mode on page 513 Clock...
Page 514 Reference Manual TIMER - Timer/Counter 19.3.3.11 Up/Down-count (Dual-slope) PWM If the counter is set to up-down count and the compare/capture channel is put in PWM mode, dual slope PWM output will be generated Figure 19.29 TIMER Up/Down-count PWM Generation on page 514.
Page 515 Reference Manual TIMER - Timer/Counter 19.3.3.12 2x Count Mode (Up/Down-count) When the timer is set in 2x mode, the TIMER will count up/down by two. This will in effect make any odd Top value be rounded down to the closest even number. Similarly, any odd OC value will generate a match on the closest lower even value as shown in Figure 19.34 TIMER CC Out in 2x mode on page 515 Clock...
Page 516 Reference Manual TIMER - Timer/Counter 19.3.3.14 Timer Configuration Lock To prevent software errors from making changes to the timer configuration, a configuration lock is available. Writing any value but 0xCE80 to LOCKKEY in TIMERn_LOCK will lock writes to TIMERn_CTRL, TIMERn_CFG, TIMERn_CMD, TIMERn_TOP, TIMERn_TOPB, TIMERn_CNT, TIMERn_CCx_CTRL, TIMERn_CCx_CFG, TIMERn_CCx_OC, and TIMERn_CCx_OCB.
Page 517: Dead-Time Insertion Unit
Reference Manual TIMER - Timer/Counter 19.3.4 Dead-Time Insertion Unit Some timer modules include a Dead-Time Insertion unit suitable for motor control applications. Refer to the device data sheet to check which timer instances have this feature. The example settings in this section are for TIMER0, but identical settings can be used for other timers with DTI as well.
Page 518 Reference Manual TIMER - Timer/Counter DTFALLT DTRISET Select Original PWM (TIM0_CCx_pre) HFPERCLK Clock control Counter TIMERn Primary output (TIMER0.CCx) Complementary Output (TIMER0.CDTIx) Figure 19.41. TIMER Overview of Dead-Time Insertion Block for a Single PWM Channel The DTI unit is enabled by setting DTEN in TIMER0_DTCFG. In addition to providing the complementary outputs, the DTI unit then also overrides the compare match outputs from the timer.
Page 519 Reference Manual TIMER - Timer/Counter Table 19.3. DTI Output When Timer Halted DTAR DTFATS State frozen safe running running 19.3.4.1 Output Polarity The value of the primary and complementary outputs in a pair will never be set active at the same time by the DTI unit. The polarity of the outputs can be changed if this is required by the application.
Page 520 Reference Manual TIMER - Timer/Counter 19.3.4.2 PRS Channel as a Source A PRS channel can be used as input to the DTI module instead of the PWM output from the timer for DTI channel 0. Setting DTPRSEN in TIMER0_DTCFG will override the source of the first DTI channel, driving TIM0_CC0 and TIM0_CDTI0, with the value on the PRS channel.
Page 521: Debug Mode
Reference Manual TIMER - Timer/Counter 19.3.4.6 DTI Configuration Lock To prevent software errors from making changes to the DTI configuration, a configuration lock is available. Writing any value but 0xCE80 to LOCKKEY in TIMER0_DTLOCK locks writes to registers TIMER0_DTCFG, TIMER0_DTFCFG, TIMER0_DTCTRL, and TIMER0_DTTIMECFG.
Page 522 Reference Manual TIMER - Timer/Counter 19.4 TIMER Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 TIMER_IPVERSION IP Version ID 0x004 TIMER_CFG RW CONFIG Configuration Register 0x008 TIMER_CTRL RW SYNC Control Register 0x00C TIMER_CMD W SYNC...
Page 523 Reference Manual TIMER - Timer/Counter Offset Name Type Description 0x1024 TIMER_CNT_SET RWH SYNC Counter Value Register 0x102C TIMER_LOCK_SET TIMER Configuration Lock Register 0x1030 TIMER_EN_SET RW ENABLE Module En 0x1060 TIMER_CCx_CFG_SET RW CONFIG CC Channel Configuration Register 0x1064 TIMER_CCx_CTRL_SET RW SYNC CC Channel Control Register 0x1068 TIMER_CCx_OC_SET...
Page 524 Reference Manual TIMER - Timer/Counter Offset Name Type Description 0x20E8 TIMER_DTFCFG_CLR RW CONFIG DTI Fault Configuration Register 0x20EC TIMER_DTCTRL_CLR RW SYNC DTI Control Register 0x20F0 TIMER_DTOGEN_CLR RW SYNC DTI Output Generation Enable Register 0x20F4 TIMER_DTFAULT_CLR DTI Fault Register 0x20F8 TIMER_DTFAULTC_CLR W SYNC DTI Fault Clear Register 0x20FC TIMER_DTLOCK_CLR...
Page 525: Timer Register Description
Reference Manual TIMER - Timer/Counter 19.5 TIMER Register Description 19.5.1 TIMER_IPVERSION - IP Version ID Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP Version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 526: Timer_Cfg - Configuration Register
Reference Manual TIMER - Timer/Counter 19.5.2 TIMER_CFG - Configuration Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 27:18 PRESC...
Page 527 Reference Manual TIMER - Timer/Counter Name Reset Access Description Value Mode Description Timer can start/stop/reload other timers with SYNC bit set Timer cannot start/stop/reload other timers with SYNC bit set RETIMEEN PWM output retimed enable Enable retiming of PWM output. Value Mode Description...
Page 528 Reference Manual TIMER - Timer/Counter Name Reset Access Description ENABLE Timer may be started, stopped and re-loaded from other timer instances. Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions MODE Timer Mode...
Page 529: Timer_Ctrl - Control Register
Reference Manual TIMER - Timer/Counter 19.5.3 TIMER_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions X2CNT 2x Count Mode...
Page 530: Timer_Cmd - Command Register
Reference Manual TIMER - Timer/Counter 19.5.4 TIMER_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions STOP W(nB)
Page 531: Timer_Status - Status Register
Reference Manual TIMER - Timer/Counter 19.5.5 TIMER_STATUS - Status Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions CCPOL2 CCn Polarity...
Page 532 Reference Manual TIMER - Timer/Counter Name Reset Access Description ICFEMPTY1 Input capture fifo empty Set when input capture FIFO is empty ICFEMPTY0 Input capture fifo empty Set when input capture FIFO is empty 15:11 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 533 Reference Manual TIMER - Timer/Counter Name Reset Access Description Counting up DOWN Counting down RUNNING Running Indicates if timer is running or not. silabs.com | Building a more connected world. Rev. 1.0 | 533...
Page 534: Timer_If - Interrupt Flag Register
Reference Manual TIMER - Timer/Counter 19.5.6 TIMER_IF - Interrupt Flag Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions ICFUF2 Input capture FIFO underflow...
Page 535 Reference Manual TIMER - Timer/Counter Name Reset Access Description In INPUT CAPTURE mode this bit indicates that a new Capture event has taken place. In OUTPUTCOMPARE or PWM mode this bit indicates that a match event has taken place Capture Compare Channel 1 Interrupt Flag In INPUT CAPTURE mode this bit indicates that a new Capture event has taken place.
Page 536: Timer_Ien - Interrupt Enable Register
Reference Manual TIMER - Timer/Counter 19.5.7 TIMER_IEN - Interrupt Enable Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:27 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions ICFUF2 ICFUF2 Interrupt Enable...
Page 537: Timer_Top - Counter Top Value Register
Reference Manual TIMER - Timer/Counter Name Reset Access Description Enable/Disable the CC1 interrupt CC0 Interrupt Enable Enable/Disable the CC0 interrupt Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions DIRCHG Direction Change Detect Interrupt Enable...
Page 538: Timer_Cnt - Counter Value Register
Reference Manual TIMER - Timer/Counter 19.5.10 TIMER_CNT - Counter Value Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:0 Counter Value These bits hold the counter value. 19.5.11 TIMER_LOCK - TIMER Configuration Lock Register Offset Bit Position 0x02C Reset Access...
Page 539: Timer_En - Module
Reference Manual TIMER - Timer/Counter 19.5.12 TIMER_EN - Module En Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions DISABLING Disablement busy status...
Page 540: Timer_Ccx_Cfg - Cc Channel Configuration Register
Reference Manual TIMER - Timer/Counter 19.5.13 TIMER_CCx_CFG - CC Channel Configuration Register Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 541 Reference Manual TIMER - Timer/Counter Name Reset Access Description This bit is only used in Output Compare and PWM mode. When this bit is set in Compare or PWM mode,the output is set high when the counter is disabled. When counting resumes, this value will represent the initial value for the output. If the bit is cleared, the output will be cleared when the counter is disabled.
Page 542: Timer_Ccx_Ctrl - Cc Channel Control Register
Reference Manual TIMER - Timer/Counter 19.5.14 TIMER_CCx_CTRL - CC Channel Control Register Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 543: Timer_Ccx_Oc - Oc Channel Value Register
Reference Manual TIMER - Timer/Counter Name Reset Access Description 11:10 COFOA Counter Overflow Output Action Select output action on counter overflow. Value Mode Description NONE No action on counter overflow TOGGLE Toggle output on counter overflow CLEAR Clear output on counter overflow Set output on counter overflow CMOA Compare Match Output Action...
Page 544: Timer_Ccx_Ocb - Oc Channel Value Buffer Register
Reference Manual TIMER - Timer/Counter 19.5.16 TIMER_CCx_OCB - OC Channel Value Buffer Register Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:0 Output Compare Value Buffer This field holds the Output Compare buffer value which will be written to TIMERn_CCx_OC on an update event if TIMERn_CCx_OCB contains valid data 19.5.17 TIMER_CCx_ICF - IC Channel Value Register Offset...
Page 545: Timer_Dtcfg - Dti Configuration Register
Reference Manual TIMER - Timer/Counter 19.5.19 TIMER_DTCFG - DTI Configuration Register Offset Bit Position 0x0E0 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions DTPRSEN DTI PRS Source Enable...
Page 546: Timer_Dttimecfg - Dti Time Configuration Register
Reference Manual TIMER - Timer/Counter 19.5.20 TIMER_DTTIMECFG - DTI Time Configuration Register Offset Bit Position 0x0E4 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 547: Timer_Dtfcfg - Dti Fault Configuration Register
Reference Manual TIMER - Timer/Counter 19.5.21 TIMER_DTFCFG - DTI Fault Configuration Register Offset Bit Position 0x0E8 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 548: Timer_Dtctrl - Dti Control Register
Reference Manual TIMER - Timer/Counter 19.5.22 TIMER_DTCTRL - DTI Control Register Offset Bit Position 0x0EC Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions DTIPOL DTI Inactive Polarity...
Page 549: Timer_Dtogen - Dti Output Generation Enable Register
Reference Manual TIMER - Timer/Counter 19.5.23 TIMER_DTOGEN - DTI Output Generation Enable Register Offset Bit Position 0x0F0 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 550: Timer_Dtfault - Dti Fault Register
Reference Manual TIMER - Timer/Counter 19.5.24 TIMER_DTFAULT - DTI Fault Register Offset Bit Position 0x0F4 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions DTEM23F DTI EM23 Entry Fault...
Page 551: Timer_Dtfaultc - Dti Fault Clear Register
Reference Manual TIMER - Timer/Counter 19.5.25 TIMER_DTFAULTC - DTI Fault Clear Register Offset Bit Position 0x0F8 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 552: Timer_Dtlock - Dti Configuration Lock Register
Reference Manual TIMER - Timer/Counter 19.5.26 TIMER_DTLOCK - DTI Configuration Lock Register Offset Bit Position 0x0FC Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 553: Usart - Universal Synchronous Asynchronous Receiver/Transmitter
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20. USART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? The USART handles high-speed UART, SPI-bus, SmartCards, and IrDA communication. Why? Serial communication is frequently used in embed- ded systems and the USART allows efficient com- munication with a wide range of external devices.
Page 554: Features
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.2 Features • Asynchronous and synchronous (SPI) communication • Full duplex and half duplex • Separate TX/RX enable • Separate receive / transmit multiple entry buffers, with additional separate shift registers • Programmable baud rate, generated as an fractional division from the peripheral clock (PCLK USARTn •...
Page 555: Functional Description
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3 Functional Description An overview of the USART module is shown in Figure 20.1 USART Overview on page 555. This section describes all posible USART features. Please refer to the Device Datasheet to see what features a specific USART in- stance supports.
Page 556: Modes Of Operation
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.1 Modes of Operation The USART operates in either asynchronous or synchronous mode. In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the main interface on the bus, and both the main and secondary devices sample and transmit data according to this clock.
Page 557 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization.
Page 558 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter The order in which the data bits are transmitted and received is defined by MSBF in USARTn_CTRL. When MSBF is cleared, data in a frame is sent and received with the least significant bit first. When it is set, the most significant bit comes first. The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the format expected by the receiver can be inverted by setting RXINV in USARTn_CTRL.
Page 559 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.3 Clock Generation The USART clock defines the transmission and reception data rate. When operating in asynchronous mode, the baud rate (bit-rate) is given by Figure 20.3 USART Baud Rate on page 559.
Page 560 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USARTn_OVS =00 USARTn_OVS =01 Desired baud USARTn_CLKDIV/256 Actual baud rate USARTn_CLKDIV/256 Actual baud rate rate [baud/s] Error % Error % (to 32nd position) [baud/s] (to 32nd position) [baud/s] 38400 38461,54 0,160 12,03125 38369,3 -0,080 57600...
Page 561 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.6 Transmit Buffer Operation The transmit-buffer is a multiple entry FIFO buffer. A frame can be loaded into the buffer by writing to USARTn_TXDATA, USARTn_TXDATAX, USARTn_TXDOUBLE or USARTn_TXDOUBLEX. Using USARTn_TXDATA allows 8 bits to be written to the buf- fer, while using USARTn_TXDOUBLE will write 2 frames of 8 bits to the buffer.
Page 562 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.7 Frame Transmission Control The transmission control bits, which can be written using USARTn_TXDATAX and USARTn_TXDOUBLEX, affect the transmission of the written frame. The following options are available: • Generate break: By setting TXBREAK, the output will be held low during the stop-bit period to generate a framing error. A receiver that supports break detection detects this state, allowing it to be used e.g.
Page 563 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.9 Receive Buffer Operation When data becomes available in the receive buffer, the RXDATAV flag in USARTn_STATUS, and the RXDATAV interrupt flag in USARTn_IF are set, and when the buffer becomes full, RXFULL in USARTn_STATUS and the RXFULL interrupt flag in USARTn_IF are set.
Page 564 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.10 Blocking Incoming Data When using hardware frame recognition, as detailed in 20.3.2.20 Multi-Processor Mode 20.3.2.21 Collision Detection, it is necessa- ry to be able to let the receiver sample incoming frames without passing the frames to software by loading them into the receive buffer. This is accomplished by blocking incoming data.
Page 565 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.11 Clock Recovery and Filtering The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling mode given by OVS in USARTn_CTRL. Lower oversampling rates make higher baud rates possible, but give less room for errors. When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame.
Page 566 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/1 Figure 20.8. USART Sampling of Stop Bits when Number of Stop Bits are 1 or More When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices.
Page 567 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.14 Local Loopback The USART receiver samples U(S)n_RX by default, and the transmitter drives U(S)n_TX by default. This is not the only option howev- er. When LOOPBK in USARTn_CTRL is set, the receiver is connected to the U(S)n_TX pin as shown in Figure 20.9 USART Local Loopback on page 567.
Page 568 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.17 Single Data-link with External Driver Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of tristating the transmitter when receiving data, the external driver must be disabled. This can be done manually by assigning a GPIO to turn the driver on or off, or it can be handled automatically by the USART.
Page 569 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.19 Large Frames As each frame in the transmit and receive buffers holds a maximum of 9 bits, both the elements in the buffers are combined when working with USART-frames of 10 or more data bits. To transmit such a frame, at least two elements must be available in the transmit buffer.
Page 570 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter When receiving a large frame, BYTESWAP in USARTn_CTRL determines the order the way the large frame is split into the two buffer elements. If BYTESWAP is cleared, the least significant 8 bits of the received frame are loaded into the first element of the receive buffer, and the remaining bits are loaded into the second element, as shown in Figure 20.13 USART Reception of Large Frames on page...
Page 571 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.2.22 SmartCard Mode In SmartCard mode, the USART supports the ISO 7816 I/O line T0 mode. With exception of the stop-bits (guard time), the 7816 data frame is equal to the regular asynchronous frame. In this mode, the receiver pulls the line low for one baud, half a baud into the guard time to indicate a parity error.
Page 572: Synchronous Operation
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 1/2 stop bit NAK or stop Stop 13 14 15 16 1 9 10 11 14 15 16 17 18 X Figure 20.16. USART SmartCard Stop Bit Sampling For communication with a SmartCard, a clock signal needs to be generated for the card. This clock output can be generated using one of the timers.
Page 573 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.3.2 Clock Generation The bit-rate in synchronous mode is given by Figure 20.17 USART Synchronous Mode Bit Rate on page 573. As in the case of asyn- chronous operation, the clock division factor have a 15-bit integral part and a 5-bit fractional part. br = f /(2 x (1 + USARTn_CLKDIV/256)) PCLK...
Page 574 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter sample clock edge if the receive buffer overflows. When a transfer has been performed, interrupt flags TXBL and TXC are updated on the first setup clock edge of the succeeding frame, or when CS is deasserted. 20.3.3.3 Synchronous Main Interface Mode When configured as a main interface, the USART is in full control of the data flow on the synchronous bus.
Page 575 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.3.6 Synchronous Secondary Interface Mode When the USART is in synchronous secondary interface mode, data transmission is not controlled by the USART, but by an external synchronous main device. The USART is therefore not able to initiate a transmission, and has no control over the number of bytes written to the external main device.
Page 576 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.3.10 Major Modes The USART supports a set of different I2S formats as shown in Table 20.9 USART I2S Modes on page 576, but it is not limited to these modes. MONO, JUSTIFY and DELAY in USARTn_I2SCTRL can be mixed and matched to create an appropriate format. MONO enables mono mode, i.e.
Page 577 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter USn_CLK USn_CS (word select) USn_TX/ USn_RX Right channel Left channel Right channel Figure 20.22. USART Left-Justified I2S Waveform A right-justified stream is shown in Figure 20.23 USART Right-Justified I2S Waveform on page 577.
Page 578: Hardware Flow Control
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.3.11 Using I2S Mode When using the USART in I2S mode, DATABITS in USARTn_FRAME must be set to 8 or 16 data-bits. 8 databits can be used in all modes, and 16 can be used in the modes where the number of bytes in the I2S word is even. In addition to this, MSBF in USARTn_CTRL should be set, and CLKPOL and CLKPHA in USARTn_CTRL should be cleared.
Page 579: Prs Clk Input
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.8 PRS CLK Input The USART can be configured to receive clock directly from a PRS channel by setting CLKPRSEN in USARTn_CTRLX. The PRS channel used is selected using PRSSEL in PRS_USARTn_CLK. This is useful in synchronous secondary mode and can together with RX PRS input be used to input data from PRS.
Page 580: Timer
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.10 Timer In addition to the TX sequence timer, there is a versatile 8 bit timer that can generate up to three event pulses. These pulses can be used to create timing for a variety of uses such as RX timeout, break detection, response timeout, and RX enable delay. Transmission delay, CS setup, inter-character spacing, and CS hold use the TX sequence counter.
Page 581 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter TIMECMP2 TIMECMP1 TIMECMP0 TCMPn TXST RXACT TCMPVALn RXACTN TSTOP GP_CNT[7:0] clear DISABLE TCMP TXEOF Compare TCMPn enable RXACT RXEOF TSTART START_An RESTARTEN START_Bn START_A2 START_B2 START_A1 start START_B1 event START_A0 8 bit bit time GP_CNT[7:0] START_B0...
Page 582 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Application TSTARTn TSTOPn TCMPVALn Other Break Detect TSTART1 = RXACT TSTOP1 = TCMPVAL1 TCMP1 in USARTn_IEN RXACTN = 0x0C TX delayed start of transmission and TSTART0 = DISA- TSTOP0 = TCMP0, TCMPVAL0 TXDELAY = TCMP0, CSSETUP = CS setup BLE, TSTART1 =...
Page 583 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.10.2 RX Timeout A receiver timeout function can be implemented by using the RX end of frame to start comparator 1 and look for the RX start bit RXACT to disable the comparator. See Table 20.10 USART Application Settings for USARTn_TIMING and USARTn_TIMECMPn on page 581 for details on setting up this example.
Page 584 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.10.4 TX Start Delay Some applications may require a delay before the start of transmission. This example in Figure 20.29 USART TXSEQ Timing on page shows the TXSEQ timer used to delay the start of transmission by 4 baud times before the start of CS, and by 2 baud times with CS asserted.
Page 585: Interrupts
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.10.8 Combined TX and RX Example This example describes how to alternate between TX and RX frames. This has a 28 baud-time space after RX and a 16 baud-time space after TX. The TSTART1 in USARTn_TIMECMP1 is set to RXEOF which uses the the receiver end of frame to start the timer. The TSTOP1 is set to TCMP1 to generate an event after 28 baud times.
Page 586: Irda Modulator/ Demodulator
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.3.12 IrDA Modulator/ Demodulator The IrDA modulator implements the physical layer of the IrDA specification, which is necessary for communication over IrDA. The mod- ulator takes the signal output from the USART module, and modulates it before it leaves the USART. In the same way, the input signal is demodulated before it enters the actual USART module.
Page 587: Usart Register Map
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.4 USART Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 USART_IPVERSION IPVERSION 0x004 USART_EN USART Enable 0x008 USART_CTRL Control Register 0x00C USART_FRAME USART Frame Format Register 0x010 USART_TRIGCTRL...
Page 588 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Offset Name Type Description 0x1020 USART_RXDATAX_SET RX Buffer Data Extended Register 0x1024 USART_RXDATA_SET RX Buffer Data Register 0x1028 USART_RXDOUBLEX_SET RX Buffer Double Data Extended Register 0x102C USART_RXDOUBLE_SET RX FIFO Double Data Register 0x1030 USART_RXDATAXP_SET RX Buffer Data Extended Peek Register...
Page 589 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Offset Name Type Description 0x2048 USART_IF_CLR RWH INTFLAG Interrupt Flag Register 0x204C USART_IEN_CLR Interrupt Enable Register 0x2050 USART_IRCTRL_CLR IrDA Control Register 0x2054 USART_I2SCTRL_CLR I2S Control Register 0x2058 USART_TIMING_CLR Timing Register 0x205C USART_CTRLX_CLR Control Register Extended 0x2060 USART_TIMECMP0_CLR...
Page 590: Usart Register Description
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5 USART Register Description 20.5.1 USART_IPVERSION - IPVERSION Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IPVERSION The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 591: Usart_Ctrl - Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.3 USART_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description SMSDELAY Synchronous Main Sample Delay Delay Synchronous Main interface sample point to the next setup edge to improve timing and allow communication at higher speeds MVDIS Majority Vote Disable...
Page 592 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description ERRSDMA Halt DMA On Error When set, DMA requests will be cleared on framing and parity errors (asynchronous mode only). Value Mode Description DISABLE Framing and parity errors have no effect on DMA requests from the USART ENABLE DMA requests from the USART are blocked while the PERR or...
Page 593 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXINV Receiver Input Invert Setting this bit will invert the input to the USART receiver. Value Mode Description DISABLE Input is passed directly to the receiver ENABLE Input is inverted before it is passed to the receiver TXBIL TX Buffer Interrupt Level Determines the interrupt and status level of the transmit buffer.
Page 594 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description IDLEHIGH The bus clock used in synchronous mode has a high base value Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 595 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description DISABLE The USART operates in asynchronous mode ENABLE The USART operates in synchronous mode silabs.com | Building a more connected world. Rev. 1.0 | 595...
Page 596: Usart_Frame - Usart Frame Format Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.4 USART_FRAME - USART Frame Format Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 597 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Each frame contains 6 data bits SEVEN Each frame contains 7 data bits EIGHT Each frame contains 8 data bits NINE Each frame contains 9 data bits Each frame contains 10 data bits ELEVEN Each frame contains 11 data bits TWELVE...
Page 598: Usart_Trigctrl - Usart Trigger Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.5 USART_TRIGCTRL - USART Trigger Control Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:13 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 599: Usart_Cmd - Command Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.6 USART_CMD - Command Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 600 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Set to activate data reception on U(S)n_RX. silabs.com | Building a more connected world. Rev. 1.0 | 600...
Page 601: Usart_Status - Usart Status Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.7 USART_STATUS - USART Status Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 602: Usart_Clkdiv - Clock Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Indicates the level of the transmit buffer. If TXBIL is 0x0, TXBL is set whenever the transmit buffer is completely empty. Otherwise TXBL is set whenever the TX Buffer becomes half full. TX Complete Set when a transmission has completed and no more data is available in the transmit buffer and shift register.
Page 603: Usart_Rxdatax - Rx Buffer Data Extended Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.9 USART_RXDATAX - RX Buffer Data Extended Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 604: Usart_Rxdoublex - Rx Buffer Double Data Extended Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.11 USART_RXDOUBLEX - RX Buffer Double Data Extended Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description FERR1 Data Framing Error 1 Set if data in buffer has a framing error. Can be the result of a break condition. PERR1 Data Parity Error 1 Set if data in buffer has a parity error (asynchronous mode only).
Page 605: Usart_Rxdouble - Rx Fifo Double Data Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.12 USART_RXDOUBLE - RX FIFO Double Data Register Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 606: Usart_Rxdoublexp - Rx Buffer Double Data Extended Peek R
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.14 USART_RXDOUBLEXP - RX Buffer Double Data Extended Peek R... Offset Bit Position 0x034 Reset Access Name Name Reset Access Description FERRP1 Data Framing Error 1 Peek Set if data in buffer has a framing error. Can be the result of a break condition. PERRP1 Data Parity Error 1 Peek Set if data in buffer has a parity error (asynchronous mode only).
Page 607: Usart_Txdatax - Tx Buffer Data Extended Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.15 USART_TXDATAX - TX Buffer Data Extended Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 608: Usart_Txdata - Tx Buffer Data Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.16 USART_TXDATA - TX Buffer Data Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 609: Usart_Txdoublex - Tx Buffer Double Data Extended Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.17 USART_TXDOUBLEX - TX Buffer Double Data Extended Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description RXENAT1 W(nB) Enable RX After Transmission Set to enable reception after transmission. TXDISAT1 W(nB) Clear TXEN After Transmission...
Page 610: Usart_Txdouble - Tx Buffer Double Data Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description First frame to write to buffer. 20.5.18 USART_TXDOUBLE - TX Buffer Double Data Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 611: Usart_If - Interrupt Flag Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.19 USART_IF - Interrupt Flag Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 612 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXFULL RX Buffer Full Interrupt Flag Set when the receive buffer becomes full. RXDATAV RX Data Valid Interrupt Flag Set when data becomes available in the receive buffer. TXBL TX Buffer Level Interrupt Flag Set when buffer becomes empty if buffer level is set to 0x0, or when the number of empty TX buffer elements equals...
Page 613: Usart_Ien - Interrupt Enable Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.20 USART_IEN - Interrupt Enable Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 614: Usart_Irctrl - Irda Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXFULL RX Buffer Full Interrupt Enable Set when the receive buffer becomes full. RXDATAV RX Data Valid Interrupt Enable Set when data becomes available in the receive buffer. TXBL TX Buffer Level Interrupt Enable Set when buffer becomes empty if buffer level is set to 0x0, or when the number of empty TX buffer elements equals...
Page 615: Usart_I2Sctrl - I2S Control Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.22 USART_I2SCTRL - I2S Control Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 616 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Set the U(S)ART in I2S mode. silabs.com | Building a more connected world. Rev. 1.0 | 616...
Page 617: Usart_Timing - Timing Register
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.23 USART_TIMING - Timing Register Offset Bit Position 0x058 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 618 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description TCMP1 Create a space of before the start of transmission for TCMPVAL1 baud-times TCMP2 Create a space of before the start of transmission for TCMPVAL2 baud-times Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 619: Usart_Ctrlx - Control Register Extended
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.24 USART_CTRLX - Control Register Extended Offset Bit Position 0x05C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 620 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Value Mode Description DISABLE Continue to transmit until TX buffer is empty ENABLE Negate RTS to stop link partner's transmission during debug HALT. NOTE** The core clock should be equal to or faster than the peripheral clock;...
Page 621: Usart_Timecmp0 - Timer Compare 0
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.25 USART_TIMECMP0 - Timer Compare 0 Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 622 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXEOF Comparator 0 and timer are started at RX end of frame 15:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 623: Usart_Timecmp1 - Timer Compare 1
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.26 USART_TIMECMP1 - Timer Compare 1 Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 624 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXEOF Comparator 1 and timer are started at RX end of frame 15:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 625: Usart_Timecmp2 - Timer Compare 2
Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter 20.5.27 USART_TIMECMP2 - Timer Compare 2 Offset Bit Position 0x068 Reset Access Name Name Reset Access Description 31:25 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 626 Reference Manual USART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXEOF Comparator 2 and timer are started at RX end of frame 15:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 627: Eusart - Universal Synchronous Asynchronous Receiver/Transmitter
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21. EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Quick Facts What? The EUSART handles high-speed UART, SPI-bus, and IrDA communication. Why? Serial communication is frequently used in embed- ded systems and the EUSART allows efficient com- munication with a wide range of external devices.
Page 628: Features
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.2 Features • Asynchronous (UART) and synchronous (SPI) communication • Full duplex and half duplex • Separate TX/RX enable • Separate receive / transmit 16 deep FIFOs, with additional separate shift registers •...
Page 629: Functional Description
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3 Functional Description An overview of the EUSART module is shown in Figure 21.1 EUSART Overview on page 629. This section describes all posible EUSART features. Please refer to the Device Datasheet to see what features a specific EUSART instance supports.
Page 630: Modes Of Operation
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.1 Modes of Operation The EUSART operates in either asynchronous or synchronous mode. In synchronous mode, a separate clock signal is transmitted with the data. This clock signal is generated by the main interface on the bus, and both the main and secondary devices sample and transmit data according to this clock.
Page 631 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.1 Frame Format The frame format used in asynchronous mode consists of a set of data bits in addition to bits for synchronization and optionally a parity bit for error checking. A frame starts with one start-bit (S), where the line is driven low for one bit-period. This signals the start of a frame, and is used for synchronization.
Page 632 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.2 Parity Bit Calculation and Handling When parity bit is enabled, hardware automatically calculates and inserts a parity bit into outgoing frames, and verifies the received parity bit in incoming frames. The possible parity modes are defined in Table 21.5 Parity Bits on page 632.
Page 633 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.3 Clock Generation The EUSART clock defines the transmission and reception data rate. The baud rate is given by Figure 21.3 EUSART Baud Rate on page 633. br = f /(oversample x (1 + EUSARTn_CLKDIV/256)) EUSARTn Figure 21.3.
Page 634 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Table 21.7. EUSART Baud Rates @ 4 MHz Peripheral Clock with 20 Bit CLKDIV EUSARTn_CFG0_OVS =00 EUSARTn_CFG0_OVS =01 Desired baud EUSARTn_CLKDIV/256 Actual baud rate EUSARTn_CLKDIV/256 Actual baud rate rate [baud/s] Error % Error (to 32nd position) [baud/s]...
Page 635 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.4 Auto Baud Detection Setting AUTOBAUDEN in EUSARTn_CFG0 uses the first frame received to automatically set the baud rate provided that it contains 0x55 (IrDA uses 0x00) and is sent out as LSB first and there is no break in the frame. AUTOBAUDEN can be used in a simple LIN configuration to auto detect the SYNC byte.
Page 636 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.5.1 Transmit FIFO Operation The transmit FIFO is a 16 deep FIFO. A frame can be loaded into the FIFO by writing to EUSARTn_TXDATA. Using EUSARTn_TXDA- TA allows 9 bits to be written to the FIFO, as well as a set of control bits regarding the transmission of the written frame. Every frame in the FIFO is stored with 9 data bits and additional transmission control bits.
Page 637 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter be cleared once TXFIW is updated). TXFL remains set as long as the underlying condition is true even if the EUSART is disabled. This means that if a software clear is done for TXFL, then the interrupt will get set again after the clear if the underlying condition is still true (this will happen even if the EUSART is disabled).
Page 638 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.6 Data Reception Data reception is enabled by setting RXEN in EUSARTn_CMD. When the receiver is enabled, it actively samples the input looking for a transition from high to low indicating the start baud of a new frame. When a start baud is found, reception of the new frame begins. When the frame has been received, it is pushed into the receive FIFO, making the shift register ready for another frame of data, and the receiver starts looking for another start baud.
Page 639 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.6.1 Receive FIFO Operation The receive-FIFO is a 16 deep FIFO. Data can be read from the receive FIFO via EUSARTn_RXDATA. EUSARTn_RXDATA gives access to the received frame. This register also contains parity error and framing error information of the received frame. When a frame is read from the receive FIFO using EUSARTn_RXDATA, the frame is pulled out of the FIFO, making room for a new frame.
Page 640 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.6.2 Blocking Incoming Data When using hardware frame recognition, as detailed in 21.3.2.6.9 Multi-Processor Mode 21.3.2.8 Collision Detection, it is necessa- ry to be able to let the receiver sample incoming frames without loading them into the receive FIFO. This is accomplished by blocking incoming data.
Page 641 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.6.3 Data Sampling and Filtering The receiver can sample incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate, depending on the oversampling mode given by OVS in EUSARTn_CFG0. Lower oversampling rates make higher baud rates possible, but give less room for errors. When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a start-bit, and the baud rate generator is synchronized with the incoming frame.
Page 642 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter n’th bit 1 stop bit Idle or start bit 13 14 15 16 1 9 10 0/1 Figure 21.9. EUSART Sampling of Stop Bits when Number of Stop Bits are 1 or More When working with stop bit lengths of half a baud period, the above sampling scheme no longer suffices.
Page 643 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.6.6 Framing Error and Break Detection A framing error is the result of an asynchronous frame where the stop bit was sampled to a value of 0. This can be the result of noise and baud rate errors, but can also be the result of a break generated by the transmitter on purpose.
Page 644 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter EUSART Multi-processor Mode Example 1. All devices on the bus enable multi-processor mode and enable and block the receiver. They will now not receive data unless it is an address frame. MPAB in EUSARTn_CFG0 is set to desired value to identify frames with the 9th bit value equal to MPAB as address frames.
Page 645 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.7 Local Loopback The EUSARTn receiver samples RX by default, and the transmitter drives TX by default. This is not the only option however. When LOOPBK in EUSARTn_CFG0 is set, the RX pin is connected to the TX pin as shown in Figure 21.11 EUSART Local Loopback on page 645.
Page 646: Debug Halt
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.9.2 Single Data-link with External Driver Some communication schemes, such as RS-485 rely on an external driver. Here, the driver has an extra input which enables it, and instead of tristating the transmitter when receiving data, the external driver must be disabled. This can be done manually by assigning a GPIO to turn the driver on or off.
Page 647 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.12 PRS-triggered Transmissions If a transmission must be started on an event with very little delay, the PRS system can be used to trigger the transmission. The PRS channel to use as a trigger can be selected using EUSARTn_TRIGGER.PRSSEL in PRS. When a positive edge is detected on PRS signal, the receiver is enabled if RXTEN in EUSARTn_TRIGCTRL is set, and the transmitter is enabled if TXTEN in EU- SARTn_TRIGCTRL is set.
Page 648 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.16 EM2 operation (EM2 Capable instance only) This is an EM2 Capable instance only feature. Even when the chip is in EM2, the EUSART (EM2 Capable instance only) can wait for an incoming EUSART frame while having an extremely low energy consumption.
Page 649 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.18.1 IRHF The IRHF modulator implements the physical layer of the IrDA specification, which is necessary for communication over IrDA. The modulator takes the signal output from the EUSART module, and modulates it before it leaves the EUSART. In the same way, the input signal is demodulated before it enters the actual EUSART module.
Page 650: Synchronous Operation
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.2.18.2 IRLF IRLF only supports RX operation. This feature will stay operational even in EM2. It is possible to cause a wake up when a certain frame is received and then switch to IRHF if TX is required. IRLFEN in IRLFCFG must be set for this to work. 21.3.3 Synchronous Operation Synchronous mode shares some common features with asynchronous mode such as: Loopback, invertion of RX/TX, MSBF, TX/RX Interrupt watermarks.
Page 651 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.3.2 Clock Generation The bit-rate in synchronous mode is given by Figure 21.14 EUSART Synchronous Mode Bit Rate on page 651. The clock division is derived from EUSARTn_CFG2.SDIV, which is applicable when acting as a Main interface only. br = f /(1 + EUSARTn_CFG2.SDIV) HFPERCLK...
Page 652 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.3.3 Main SPI Interface Mode When configured as a main interface, the EUSART is in full control of the data flow on the synchronous bus. When operating in full duplex mode, the secondary devices cannot transmit data to the main device without the main device transmitting to the secondary. The main device outputs the bus clock on SCLK.
Page 653: Prs-Triggered Transmissions
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.3.6 Secondary SPI Interface Mode When the EUSART is in secondary interface mode, data transmission is not controlled by the EUSART, but by an external main SPI device. The EUSART is therefore not able to initiate a transmission, and has no control over the number of bytes written to the external main device.
Page 654: Prs Rx Input
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.3.6 PRS RX Input The EUSART can be configured to receive data directly from a PRS channel by setting RXPRS in EUSARTn_INPUT. The PRS channel used is selected using RXPRSSEL in EUSARTn_INPUT. This way, for example, a differential RX signal can be input to the ACMP and the output routed via PRS to the EUSART.
Page 655: Eusart Register Map
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.4 EUSART Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 EUSART_IPVERSION IP Version ID 0x004 EUSART_EN RW ENABLE Enable Register 0x008 EUSART_CFG0 RW CONFIG Configuration 0 Register 0x00C...
Page 656 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Offset Name Type Description 0x1030 EUSART_CLKDIV_SET RWH LFSYNC Clock Divider Register 0x1034 EUSART_TRIGCTRL_SET RW LFSYNC Trigger Control Register 0x1038 EUSART_CMD_SET W LFSYNC Command Register 0x103C EUSART_RXDATA_SET RX Data Register 0x1040 EUSART_RXDATAP_SET RX Data Peek Register 0x1044 EUSART_TXDATA_SET TX Data Register...
Page 657: Eusart Register Description
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Offset Name Type Description 0x3010 EUSART_CFG2_TGL RW CONFIG Configuration 2 Register 0x3014 EUSART_FRAMECFG_TGL RW CONFIG Frame Format Register 0x3018 EUSART_DTXDATCFG_TGL RW CONFIG Default TX DATA Register 0x301C EUSART_IRHFCFG_TGL RW CONFIG HF IrDA Mod Config Register 0x3020 EUSART_IRLFCFG_TGL RW CONFIG...
Page 658: Eusart_En - Enable Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.2 EUSART_EN - Enable Register Offset Bit Position 0x004 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 659: Eusart_Cfg0 - Configuration 0 Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.3 EUSART_CFG0 - Configuration 0 Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description AUTOBAUDEN AUTOBAUD detection enable Detects the baud rate based on receiving a 0x55 frame (0x00 for IrDA). Only applicable when CFG0.SYNC bit is set to 'ASYNC'.
Page 660 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description SKIPPERRF Skip Parity Error Frames When set, the receiver discards frames with parity errors. The PERR interrupt flag is still set. Only applicable when CFG0.SYNC bit is set to 'ASYNC'. 19:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un-...
Page 661 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description 16X oversampling 8X oversampling 6X oversampling 4X oversampling DISABLE Disable oversampling (for LF operation) MPAB Multi-Processor Address-Bit Defines the value of the multi-processor address bit. An incoming frame with its 9th bit equal to the value of this bit marks the frame as a multi-processor address frame.
Page 662: Eusart_Cfg1 - Configuration 1 Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.4 EUSART_CFG1 - Configuration 1 Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 663 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description FIFTEENFRAMES RXFL status flag and IF are set when the RX FIFO has at least fifteen frames in it. SIXTEENFRAMES RXFL status flag and IF are set when the RX FIFO has at least sixteen frames in it.
Page 664 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description ONEFRAME TXFL status flag and IF are set when the TX FIFO has space for at least one more frame. TWOFRAMES TXFL status flag and IF are set when the TX FIFO has space for at least two more frames.
Page 665 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions RXTIMEOUT RX Timeout When enabled, determines how long, in units of frame, RX needs to remain idle after a frame reception before RXTOIF gets set.
Page 666 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description ENABLE If core is halted, receive one frame and then halt reception by deactivating RTS. Next frame reception happens when the core is unhalted during single stepping. silabs.com | Building a more connected world. Rev.
Page 667: Eusart_Cfg2 - Configuration 2 Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.5 EUSART_CFG2 - Configuration 2 Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:24 SDIV Sync Clock Div Sets the clock rate for synchronous main mode operation only (To set the clock rate for asynchronous operation, see the CLKDIV field).
Page 668 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Determines where data is set-up and sampled according to the bus clock when in synchronous mode. Only applicable when CFG0.SYNC bit is set to 'SYNC'. Value Mode Description SAMPLELEADING Data is sampled on the leading edge and set-up on the trailing edge of the bus clock in synchronous mode...
Page 669: Eusart_Framecfg - Frame Format Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.6 EUSART_FRAMECFG - Frame Format Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 670: Eusart_Dtxdatcfg - Default Tx Data Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description NINE Each frame contains 9 data bits Each frame contains 10 data bits ELEVEN Each frame contains 11 data bits TWELVE Each frame contains 12 data bits THIRTEEN Each frame contains 13 data bits FOURTEEN Each frame contains 14 data bits...
Page 671: Eusart_Irhfcfg - Hf Irda Mod Config Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.8 EUSART_IRHFCFG - HF IrDA Mod Config Register Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 672: Eusart_Irlfcfg - Lf Irda Pulse Config Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.9 EUSART_IRLFCFG - LF IrDA Pulse Config Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 673: Eusart_Timingcfg - Timing Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.10 EUSART_TIMINGCFG - Timing Register Offset Bit Position 0x024 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 674 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description ZERO CS is de-asserted half or 1 baud-time after the end of transmis- sion depending on CLKPHASE equal to 1 or 0 respectively CS is de-asserted 1 additional baud-time after the end of trans- mission CS is de-asserted 2 additional baud-times after the end of trans- mission...
Page 675: Eusart_Startframecfg - Start Frame Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description NONE Frames are transmitted immediately. SINGLE Transmission of new frames is delayed by a single bit period. DOUBLE Transmission of new frames is delayed by a two bit periods. TRIPPLE Transmission of new frames is delayed by a three bit periods.
Page 676: Eusart_Clkdiv - Clock Divider Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.13 EUSART_CLKDIV - Clock Divider Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:23 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 677: Eusart_Cmd - Command Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.15 EUSART_CMD - Command Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 678: Eusart_Rxdata - Rx Data Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.16 EUSART_RXDATA - RX Data Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 679: Eusart_Txdata - Tx Data Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.18 EUSART_TXDATA - TX Data Register Offset Bit Position 0x044 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 680: Eusart_Status - Status Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.19 EUSART_STATUS - Status Register Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 681 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Set when the transmitter is tristated, and cleared when transmitter output is enabled. If AUTOTRI in UARTn_CFG is set, then this bit is always read as 0. Only applicable when CFG0.SYNC bit is set to 'ASYNC'. RXBLOCK Block Incoming Data When set, the receiver discards incoming frames.
Page 682: Eusart_If - Interrupt Flag Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.20 EUSART_IF - Interrupt Flag Register Offset Bit Position 0x04C Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 683 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description Set when the empty TX FIFO is loaded less than the required TIMINGCFG.SETUPWINDOW bus clock cycles before the first edge of the incoming SCLK. Only applicable when CFG0.SYNC bit is set to 'SYNC' and CFG2.MASTER is set to 'SLAVE' and CFG2.FORCELOAD is set.
Page 684: Eusart_Ien - Interrupt Enable Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.21 EUSART_IEN - Interrupt Enable Register Offset Bit Position 0x050 Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 685 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description PERR Parity Error IEN Interrupt enable for PERRIF. TXUF TX FIFO Underflow IEN Interrupt enable for TXUFIF. TXOF TX FIFO Overflow IEN Interrupt enable for TXOFIF. RXUF RX FIFO Underflow IEN Interrupt enable for RXUFIF.
Page 686: Eusart_Syncbusy - Synchronization Busy Register
Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter 21.5.22 EUSART_SYNCBUSY - Synchronization Busy Register Offset Bit Position 0x054 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 687 Reference Manual EUSART - Universal Synchronous Asynchronous Receiver/Transmitter Name Reset Access Description RXTEN SYNCBUSY for RXTEN in TRIGCTRL This bit is set when there is an ongoing synchronization of RXTEN field. Do not do another write to the same field while this bit is set.
Page 688: I2C - Inter-Integrated Circuit Interface
Reference Manual I2C - Inter-Integrated Circuit Interface 22. I2C - Inter-Integrated Circuit Interface Quick Facts What? The I C interface allows communication on I buses with the lowest energy consumption possible. Why? C is a popular serial bus that enables communica- tion with a number of external devices using only Gecko Device C leader/follower...
Page 689: Functional Description
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3 Functional Description An overview of the I2C module is shown in Figure 22.1 I2C Overview on page 689. Peripheral Bus C Control and Transmit Buffer Receive Buffer Status (2-level FIFO) (2-level FIFO) I2Cn_SDA Symbol Transmit...
Page 690: I2C-Bus Overview
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.1 I2C-Bus Overview The I C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as shown in Figure 22.2 I2C-Bus Example on page 690. As a true multi-leader bus it includes collision detection and arbitration to resolve situations where multiple leaders transmit data at the same time without data loss.
Page 691 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.1.1 START and STOP Conditions START and STOP conditions are used to initiate and stop transactions on the I C-bus. All transactions on the bus begin with a START condition (S) and end with a STOP condition (P). As shown in Figure 22.4 I2C START and STOP Conditions on page 691, a START condition is generated by pulling the SDA line low while SCL is high, and a STOP condition is generated by pulling the SDA line high...
Page 692 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.1.2 Bus Transfer When a leader wants to initiate a transfer on the bus, it waits until the bus is idle and transmits a START condition on the bus. The leader then transmits the address of the follower it wishes to interact with and a single R/W bit telling whether it wishes to read from the follower (R/W bit set to 1) or write to the follower (R/W bit set to 0).
Page 693 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.1.3 Addresses C supports both 7-bit and 10-bit addresses. When using 7-bit addresses, the first byte transmitted after the START-condition contains the address of the follower that the leader wants to contact. In the 7-bit address space, several addresses are reserved. These ad- dresses are summarized in Table 22.1 I2C Reserved I C Addresses on page...
Page 694: Enable And Reset
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.1.5 Arbitration, Clock Synchronization, Clock Stretching Arbitration and clock synchronization are features aimed at allowing multi-leader buses. Arbitration occurs when two devices try to drive the bus at the same time. If one device drives it low, while the other drives it high, the one attempting to drive it high will not be able to do so due to the open-drain bus configuration.
Page 695: Clock Generation
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.5 Clock Generation The I C peripheral clock (I2CCLK) for I2C0 is derived from the LSPCLK, and for I2C1 is derived from the PCLK. The SCL signal generated by the I C leader determines the maximum transmission rate on the bus. The clock is generated as a divi- sion of the peripheral clock (I2CCLK), and is given by the following equation: /(((N ) x (DIV + 1)) + 8 + N...
Page 696 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.7.1 Transmit Buffer and Shift Register The I C transmitter has a 2-level FIFO transmit buffer and a transmit shift register as shown in Figure 22.1 I2C Overview on page 689. A byte is loaded into the transmit buffer by writing to I2C_TXDATA or 2 bytes can be loaded simultaneously in the transmit buffer by writing to I2C_TXDOUBLE.
Page 697 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.7.2 Receive Buffer and Shift Register The I C receiver uses a 2-level FIFO receive buffer and a receive shift register as shown in Figure 22.15 I2C Receive Buffer Operation on page 697. When a byte has been fully received by the receive shift register, it is loaded into the receive buffer if there is room for it, making the shift register empty to receive another byte.
Page 698: Leader Operation
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.8 Leader Operation A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting the START bit in I2C_CMD. The command schedules a START condition, and makes the I C module generate a start condition whenever the bus becomes free.
Page 699 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.8.1 Leader State Machine The leader state machine is shown in Figure 22.16 I2C Leader State Machine on page 699. A leader operation starts in the far left of the state machine, and follows the solid lines through the state machine, ending the operation or continuing with a new operation when arriving at the right side of the state machine.
Page 700 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.8.2 Interactions Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing all bus activities, and the BUSHOLD interrupt flag in I2C_IF is set. The action(s) required by software depends on the current state the of the I C module.
Page 701 Reference Manual I2C - Inter-Integrated Circuit Interface When several interactions are possible from a set of pending commands, the interaction with the highest priority, i.e., the interaction closest to the top of Table 22.2 I2C Interactions in Prioritized Order on page 700 is applied to the bus.
Page 702 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.8.5 Leader Transmitter To transmit data to a follower, the leader must operate as a leader transmitter. Table 22.3 I2C Leader Transmitter on page 702 shows the states the I C module goes through while acting as a leader transmitter. Every state where an interaction is required has the possi- ble interactions listed, along with the result of the interactions.
Page 703 Reference Manual I2C - Inter-Integrated Circuit Interface I2C_STATE Description I2C_IF Required in- Response teraction 0x97 ADDR+W transmitted, ACK interrupt flag TXDATA DATA will be sent ACK received (BUSHOLD interrupt STOP STOP will be sent. Bus will be released flag) START Repeated start condition will be sent STOP + STOP will be sent and the bus released.
Page 704 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.8.6 Leader Receiver To receive data from a follower, the leader must operate as a leader receiver, see Table 22.4 I2C Leader Receiver on page 704. This is done by transmitting ADDR+R as the address byte instead of ADDR+W, which is transmitted to become a leader transmitter. The address byte loaded into the data register thus has to contain the 7-bit follower address in the 7 most significant bits of the byte, and have the least significant bit set.
Page 705 Reference Manual I2C - Inter-Integrated Circuit Interface I2C_STATE Description I2C_IF Required in- Response teraction 0xB3 Data received RXDATA interrupt ACK + RXDA- ACK will be transmitted, reception continues flag(BUSHOLD inter- rupt flag) NACK + NACK will be transmitted, reception continues CONT + RXDATA ACK/NACK +...
Page 706: Bus States
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.9 Bus States The I2C_STATE register can be used to determine which state the I C module and the I C bus are in at a given time. The register consists of the STATE bit-field, which shows which state the I C module is at in any ongoing transmission, and a set of single-bits, which reveal the transmission mode, whether the bus is busy or idle, and whether the bus is held by this I C module waiting for a soft-...
Page 707 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.10.1 Follower State Machine The follower state machine is shown in Figure 22.17 I2C Follower State Machine on page 707. The dotted lines show where I specific interrupt flags are set. The full-drawn circles show places where interaction may be required by software to let the transmission proceed.
Page 708 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.10.3 Follower Transmitter When SLAVE in I2C_CTRL is set, the RSTART interrupt flag in I2C_IF will be set when repeated START conditions are detected. After a START or repeated START condition, the bus leader will transmit an address along with an R/W bit. If there is no room in the receive shift register for the address, the bus will be held by the follower until room is available in the shift register.
Page 709 Reference Manual I2C - Inter-Integrated Circuit Interface I2C_STATE Description I2C_IF Required in- Response teraction Stop received SSTOP interrupt flag None The follower goes idle START START will be sent when bus becomes idle Arbitration lost ARBLOST interrupt flag None The follower goes idle START START will be sent when the bus becomes idle silabs.com | Building a more connected world.
Page 710: Transfer Automation
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.10.4 Follower Receiver A follower receiver operation is started in the same way as a follower transmitter operation, with the exception that the address trans- mitted by the leader has the R/W bit cleared (W), indicating that the leader wishes to write to the follower. The follower then goes into follower receiver mode.
Page 711: Using 10-Bit Addresses
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.11.1 DMA DMA can be used to automatically load data into the transmit buffer and load data out from the receive buffer. When using DMA, soft- ware is thus relieved of moving data to and from memory after each transferred byte. 22.3.11.2 Automatic ACK When AUTOACK in I2C_CTRL is set, an ACK is sent automatically whenever an ACK interaction is possible and no higher priority interactions are pending.
Page 712 Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.13.2 Bus Reset A bus reset can be performed by setting the START and STOP commands in I2C_CMD while the transmit buffer is empty. A START condition will then be transmitted, immediately followed by a STOP condition. A bus reset can also be performed by transmitting a START command with the transmit buffer empty and AUTOSE set.
Page 713: Dma Support
Reference Manual I2C - Inter-Integrated Circuit Interface 22.3.13.7 Clock Low Error The I C module can continue transmission in parallel with another device for the entire transaction, as long as the two communications are identical. A case may arise when (before an arbitration has been decided upon) the I C module decides to send out a repeated START or a STOP condition while the other device is still sending data.
Page 714: I2C Register Map
Reference Manual I2C - Inter-Integrated Circuit Interface 22.4 I2C Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 I2C_IPVERSION IP VERSION Register 0x004 I2C_EN Enable Register 0x008 I2C_CTRL Control Register 0x00C I2C_CMD Command Register 0x010...
Page 715 Reference Manual I2C - Inter-Integrated Circuit Interface Offset Name Type Description 0x2004 I2C_EN_CLR Enable Register 0x2008 I2C_CTRL_CLR Control Register 0x200C I2C_CMD_CLR Command Register 0x2010 I2C_STATE_CLR State Register 0x2014 I2C_STATUS_CLR Status Register 0x2018 I2C_CLKDIV_CLR Clock Division Register 0x201C I2C_SADDR_CLR Follower Address Register 0x2020 I2C_SADDRMASK_CLR Follower Address Mask Register...
Page 716: I2C Register Description
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5 I2C Register Description 22.5.1 I2C_IPVERSION - IP VERSION Register Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 717: I2C_Ctrl - Control Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.3 I2C_CTRL - Control Register Offset Bit Position 0x008 Reset Access Name Name Reset Access Description 31:22 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 718 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description I2C1024PCC Timeout after 1024 prescaled clock cycles. In standard mode at 100 kHz, this results in a 1280us timeout. GIBITO Go Idle on Bus Idle Timeout When set, the bus automatically goes idle on a bus idle timeout, allowing new transfers to be initiated. Value Mode Description...
Page 719 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description HALF_FULL TXBL status and the TXBL interrupt flag are set when the trans- mit buffer goes from full to half-full or empty. TXBL is cleared when the buffer becomes full GCAMEN General Call Address Match Enable Set to enable address match on general call in addition to the programmed follower address.
Page 720 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set this bit to allow the device to be selected as an I2C follower. Value Mode Description DISABLE All addresses will be responded to with a NACK ENABLE Addresses matching the programmed follower address or the general call address (if enabled) require a response from soft- ware.
Page 721: I2C_Cmd - Command Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.4 I2C_CMD - Command Register Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 722: I2C_State - State Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.5 I2C_STATE - State Register Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 723: I2C_Status - Status Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.6 I2C_STATUS - Status Register Offset Bit Position 0x014 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 724: I2C_Clkdiv - Clock Division Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.7 I2C_CLKDIV - Clock Division Register Offset Bit Position 0x018 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 725: I2C_Saddrmask - Follower Address Mask Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.9 I2C_SADDRMASK - Follower Address Mask Register Offset Bit Position 0x020 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 726: I2C_Rxdouble - Receive Buffer Double Data Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.11 I2C_RXDOUBLE - Receive Buffer Double Data Register Offset Bit Position 0x028 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 727: I2C_Rxdoublep - Receive Buffer Double Data Peek Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.13 I2C_RXDOUBLEP - Receive Buffer Double Data Peek Register Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 728: I2C_Txdouble - Transmit Buffer Double Data Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.15 I2C_TXDOUBLE - Transmit Buffer Double Data Register Offset Bit Position 0x038 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 729: I2C_If - Interrupt Flag Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.16 I2C_IF - Interrupt Flag Register Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 730 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP condition, then the MSTOP interrupt flag is not set. NACK Not Acknowledge Received Interrupt Flag Set when a NACK has been received.
Page 731: I2C_Ien - Interrupt Enable Register
Reference Manual I2C - Inter-Integrated Circuit Interface 22.5.17 I2C_IEN - Interrupt Enable Register Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:21 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 732 Reference Manual I2C - Inter-Integrated Circuit Interface Name Reset Access Description Set when a STOP condition has been successfully transmitted. If arbitration is lost during the transmission of the STOP condition, then the MSTOP interrupt flag is not set. NACK Not Acknowledge Received Interrupt Flag Set when a NACK has been received.
Page 733: Iadc - Incremental Analog To Digital Converter
Reference Manual IADC - Incremental Analog to Digital Converter 23. IADC - Incremental Analog to Digital Converter Quick Facts What? The IADC is used to convert analog voltages into a digital representation and features high-speed, low- power operation. Why? In many applications there is a need to measure an- alog signals and record them in a digital representa- tion, without exhausting the energy source.
Page 734: Features
Reference Manual IADC - Incremental Analog to Digital Converter 23.2 Features • Flexible oversampled architecture allows for tradeoffs between speed and resolution. • 1 Msps with oversampling ratio = 2 • 555 ksps with oversampling ratio = 4 • 76.9 ksps with oversampling ratio = 32 •...
Page 735: Functional Description
Reference Manual IADC - Incremental Analog to Digital Converter • Available interrupt sources: • Single FIFO has DVL (data valid level) entries available (also generates DMA request) • Scan FIFO has DVL (data valid level) entries available (also generates DMA request) •...
Page 736: Register Access
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.1 Register Access Many of the IADC module's configuration registers can only be written while the module is disabled (IADC_EN_EN = 0). These are IADC_CTRL, IADC_TIMER, IADC_CMPTHR, IADC_TRIGGER, IADC_CFGx, IADC_SCALEx, IADC_SCHEDx, and IADC_SCANx. A typical setup sequence for the IADC module is: 1.
Page 737: Clocking
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.2 Clocking The IADC logic is partitioned into two clock domains: CLK_BUS (APBIF) and CLK_SRC_ADC (CORE). The APBIF domain contains the IADC registers and FIFO read logic. The rest of the IADC is clocked mainly by CLK_SRC_ADC and ADC_CLK, both of which are de- rived from CLK_CMU_ADC, as shown in Figure 23.2 Clocking on page 737.
Page 738: Conversion Timing
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.3 Conversion Timing The IADC takes multiple samples of the analog signal to produce each output. The number of input samples contributing to an output word is determined by the oversampling ratio (OSR). Higher OSR settings will improve the ADC's INL and DNL, and reduce system- level noise, but require more time for each conversion.
Page 739 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.3.2 Conversion Pipeline The IADC uses a pipelined architecture to perform different stages of the ADC conversion in parallel. The conversion time for a single sample can be determined from the OSR and the pre-scaled CLK_ADC frequency (f ) as: CLK_ADC Conversion Time = ((4 * OSR) + 2) / f...
Page 740 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.3.3 Scheduling and Triggers The IADC has several triggering options available for both the Single queue and the Scan queue. When a conversion trigger occurs and there are no other conversions active or pending, the request is serviced immediately. If both the single and scan queues are being used in an application, it is possible to serve the conversion requests as needed, and specify their priority.
Page 741 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.3.3.1 Conversion Triggering Examples Scheduling a Single Sample The simplest use case for the IADC is performing one conversion on-demand from the Single queue. Figure 23.5 Immediate Single Conversion on page 741 shows the configuration and timing of this use case.
Page 742 Reference Manual IADC - Incremental Analog to Digital Converter Periodic Scans Another common use case is to periodically trigger the IADC to perform a multi-channel scan. Figure 23.6 Periodic Scan Example on page 742 shows the timing of a periodic scan triggered by the IADC's local timer. The scanner is configured to sample four different channels;...
Page 743 Reference Manual IADC - Incremental Analog to Digital Converter Tailgating Examples An example using conversion tailgating is shown in Figure 23.7 Simple Conversion with Tailgating Enabled on page 743. In the ex- ample, the Scan queue is configured to trigger a two-channel conversion periodically on the IADC local timer, while the Single queue is configured to trigger on-demand from software.
Page 744 Reference Manual IADC - Incremental Analog to Digital Converter SINGLE and SCAN use different triggers PRS pushes out TMR timing sample TIMER PRS1 SCANQEN SINGLEQEN positive negative QUEUE mask port port Trigger Source trigger action SCAN INTERNAL TIMER once SINGLE PRSPOS once warmup, or changing between configurations...
Page 745: Reference Selection And Analog Gain
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.4 Reference Selection and Analog Gain The default IADC reference is to use the internal band gap circuit. The analog power supply voltage can also be used as a voltage reference. The reference voltage is selected using the REFSEL field in IADC_CFGx. Table 23.1.
Page 746: Input And Configuration Selection
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.5 Input and Configuration Selection The IADC supports measurement on a number of internal and external signals. External signals are routed to GPIO through shared ABUS resources on the device, or (on some devices) through dedicated analog inputs available to the IADC block. The single queue and the scan queue have separate registers available to select inputs and configurations.
Page 747 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.5.2 Internal and Dedicated Inputs Internal signals and dedicated inputs are not routed through the shared ABUS resources. In general, these resources are selected di- rectly by the settings of PORTPOS and PORTNEG, while the PINPOS and PINNEG fields are not used. When PORTPOS is set to SUPPLY, PINPOS is used to select which of the power supplies is connected.
Page 748 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.5.3 ABUS Input Selection Examples When configuring to measure a single-ended signal through the ABUS, the positive input selection should always point to the desired input, and PORTNEG should be programmed to GND. Correct configuration examples for single-ended conversions are shown in Figure 23.10 Single-Ended Port/Pin Selection Odd Channel on page 748...
Page 749 Reference Manual IADC - Incremental Analog to Digital Converter Single Ended Polarity Error GPIOCTRL: Positive Negative CD_ODD1 to ADC port port A_EVEN0 A_EVEN1 even VINT=GND CD_ODD0 Result = CD_ODD1 POLARITYERROR Single Ended is only allowed on positive side Figure 23.12. Single-Ended Port/Pin Selection Polarity Error Correct configuration examples for differential conversions are shown in Figure 23.13 Differential Port/Pin Selection without Swap on page 749...
Page 750 Reference Manual IADC - Incremental Analog to Digital Converter Differential GPIOCTRL: A_EVEN0 to ADC Positive Negative CD_ODD0 to ADC port port A0_EVEN A1_EVEN even C0_ODD C1_ODD Figure 23.14. Differential Port/Pin Selection with Swap Figure 23.15 Differential Port/Pin Selection Polarity Error on page 750 shows an example where the both the positive and the nega- tive input selections point to ODD buses.
Page 751: Gain And Offset Correction
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.5.4 Scan Queue The scan queue allows the IADC to automatically convert up to 16 channels in sequence without CPU intervention. Input and configura- tion selection for each channel in the scan table is specified by the IADC_SCANx register for that channel (channel 0 is configured with IADC_SCAN0, channel 1 is configured with IADC_SCAN1, and so on).
Page 752 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.6.1.1 Gain Correction The IADC gain error is designed to be minimal with the digital gain correction set to 1.0 (GAIN3MSB = 1 and GAIN13LSB = 0). Tighter gain error is achieved by adjusting these values in IADC_SCALEx. Using this gain correction mechanism will result in a slight increase to the DNL of the converter, which is reduced by higher OSR settings.
Page 753 Reference Manual IADC - Incremental Analog to Digital Converter The production offset calibration consists of four 16-bit terms written to the DEVINFO space: OFFSETANA1NORM, OFFSETA- NA2NORM, OFFSETANA3NORM, and OFFSETANABASE. The following procedures will determine the setting for the OFFSET regis- ter based on production calibration values.
Page 754 Reference Manual IADC - Incremental Analog to Digital Converter off_sys = 640*(256/OSR) Total uncorrected offset (off_tot) is calculated by: off_tot = (off_ana * 4 + off_sys) Step 5: Apply gain error correction, if needed. Before writing the OFFSET field, the total uncorrected offset must be multiplied by the gain calibration factor. If the gain calibration fac- tor is equal to 1.0 (0x8000 in 16-bit hex, or GAIN3MSB = 1 and GAIN13LSB = 0), this step may be skipped.
Page 755: Output Data Fifos
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.7 Output Data FIFOs The single and scan queues each have a eight-word data FIFO. Conversions results are written to the output data FIFO associated with the queue. Single queue results are written to the single FIFO and scan queue results are written to the scan data FIFO. The two queues are identical in operation, but independent.
Page 756 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.7.1 Data Alignment and Channel ID The IADC has data alignment options and the ability to include a channel ID along with the conversion data. For the single queue, alignment and channel ID are configured in the IADC_SINGLEFIFOCFG register. For the scan queue, alignment and channel ID are configured in the IADC_SCANFIFOCFG register.
Page 757 Reference Manual IADC - Incremental Analog to Digital Converter 23.3.7.2 Output Polarity The output polarity of the IADC is controlled by the TWOSCOMPL field in the IADC_CFGx register. The IADC supports unipolar and bipolar output formatting independent of the input configuration. By default, the TWOSCOMPL field is set to AUTO, meaning that sin- gle-ended conversions will produce unipolar output, and differential conversions will produce bipolar output.
Page 758: Window Compare
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.8 Window Compare The IADC has a window comparison unit that can trigger interrupts conditional on the output data of the converter. The window compar- ison unit has two thresholds - greater than or equal (ADGT), and less than or equal (ADLT), which are programmable through the IADC_CMPTHR register.
Page 759: Interrupts
Reference Manual IADC - Incremental Analog to Digital Converter 23.3.9 Interrupts Interrupts are enabled in the IADC_IEN register, allowing interrupts to be generated on several different IADC conditions. Each of the flags in IADC_IF has a corresponding enable bit in the IADC_IEN register. A brief overview of the available interrupt sources is shown in the list below;...
Page 760: Iadc Register Map
Reference Manual IADC - Incremental Analog to Digital Converter 23.4 IADC Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 IADC_IPVERSION IPVERSION 0x004 IADC_EN RW ENABLE Enable 0x008 IADC_CTRL RW CONFIG Control 0x00C IADC_CMD...
Page 761 Reference Manual IADC - Incremental Analog to Digital Converter Offset Name Type Description 0x1028 IADC_IEN_SET Interrupt Enable 0x102C IADC_TRIGGER_SET RW CONFIG Trigger 0x1048 IADC_CFGx_SET RW CONFIG Configuration 0x1050 IADC_SCALEx_SET RW CONFIG Scaling 0x1054 IADC_SCHEDx_SET RW CONFIG Scheduling 0x1070 IADC_SINGLEFIFOCFG_SET RW CONFIG Single FIFO Configuration 0x1074 IADC_SINGLEFIFODATA_SET...
Page 762 Reference Manual IADC - Incremental Analog to Digital Converter Offset Name Type Description 0x208C IADC_SCANDATA_CLR RH SYNC Scan Data 0x2098 IADC_SINGLE_CLR RW SYNC Single Queue Port Selection 0x20A0 IADC_SCANx_CLR RW CONFIG SCAN Entry 0x3000 IADC_IPVERSION_TGL IPVERSION 0x3004 IADC_EN_TGL RW ENABLE Enable 0x3008 IADC_CTRL_TGL...
Page 763: Iadc Register Description
Reference Manual IADC - Incremental Analog to Digital Converter 23.5 IADC Register Description 23.5.1 IADC_IPVERSION - IPVERSION Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION IP version ID The read only IPVERSION field gives the version for this module. There may be minor software changes required for modules with different values of IPVERSION.
Page 764: Iadc_Ctrl - Control
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.3 IADC_CTRL - Control Offset Bit Position 0x008 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 765 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description ADC behavior when halted by debugger. Value Mode Description NORMAL Continue operation as normal during debug mode HALT Complete the current conversion and then halt during debug mode ADCCLKSUSPEND1 ADC_CLK Suspend - PRS1...
Page 766: Iadc_Cmd - Command
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.4 IADC_CMD - Command Offset Bit Position 0x00C Reset Access Name Name Reset Access Description 31:26 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 767: Iadc_Timer - Timer
Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description Start the Single queue. Enables triggering of the Single queue. 23.5.5 IADC_TIMER - Timer Offset Bit Position 0x010 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 768: Iadc_Status - Status
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.6 IADC_STATUS - Status Offset Bit Position 0x014 Reset Access Name Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 769: Iadc_Maskreq - Mask Request
Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description 13:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions SCANFIFODV SCANFIFO Data Valid At least one result in the scan FIFO is ready to read.
Page 770: Iadc_Stmask - Scan Table Mask
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.8 IADC_STMASK - Scan Table Mask Offset Bit Position 0x01C Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 771: Iadc_If - Interrupt Flags
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.10 IADC_IF - Interrupt Flags Offset Bit Position 0x024 Reset Access Name Name Reset Access Description EM23ABORTERROR EM2/3 Abort Error The system entered EM2 or EM3 during a conversion with an unsupported clock. Conversion results may be corrupted. 30:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un-...
Page 772 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions SCANCMP Scan Result Window Compare Scan digital compare window tripped.
Page 773: Iadc_Ien - Interrupt Enable
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.11 IADC_IEN - Interrupt Enable Offset Bit Position 0x028 Reset Access Name Name Reset Access Description EM23ABORTERROR EM2/3 Abort Error Enable EM2/3 Abort Error Enable 30:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 774 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions SCANCMP Scan Result Window Compare Enable Scan Result Window Compare Enable SINGLECMP Single Result Window Compare Enable...
Page 775: Iadc_Trigger - Trigger
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.12 IADC_TRIGGER - Trigger Offset Bit Position 0x02C Reset Access Name Name Reset Access Description 31:17 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 776 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description IMMEDIATE Immediate triggering. The single queue will be disabled once the conversion is complete, unless TRIGGERACTION is set to continuous. TIMER Triggers when the local timer count reaches zero. PRSCLKGRP Triggers on PRS1 from a timer module that is using the same clock group as the ADC and has been programmed to use the...
Page 777 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description PRSPOS Triggers on asynchronous PRS0 positive edge. Requires PRS0 to go low for 3 ADC_CLKs before another positive edge can be detected. Generates an additional delay of 1 to 2 ADC_SRC_CLK cycles for synchronization.
Page 778: Iadc_Cfgx - Configuration
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.13 IADC_CFGx - Configuration Offset Bit Position 0x048 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 779 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description VREF External Reference. (Calibrated for 1.25V nominal.) VDDX AVDD (unbuffered) VDDX0P8BUF AVDD (buffered) * 0.8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 780: Iadc_Scalex - Scaling
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.14 IADC_SCALEx - Scaling Offset Bit Position 0x050 Reset Access Name Name Reset Access Description GAIN3MSB Gain 3 MSBs 3 MSBs of the 16-bit gain value (0=011 or 0.75; 1=1xx or 1.00). Example {GAIN3MSB, GAIN13LSB} = {100, 0_1001_0000_0000} = 1.07031x.
Page 781: Iadc_Singlefifocfg - Single Fifo Configuration
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.16 IADC_SINGLEFIFOCFG - Single FIFO Configuration Offset Bit Position 0x070 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 782: Iadc_Singlefifodata - Single Fifo Data
Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description VALID8 When 8 entries in the single FIFO are valid, set the SINGLEFI- FODVL interrupt and request DMA. SHOWID Show ID ID of 0x20 will be applied in the output words. ALIGNMENT Alignment Alignment of output data written into FIFO.
Page 783: Iadc_Singlefifostat - Single Fifo Status
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.18 IADC_SINGLEFIFOSTAT - Single FIFO Status Offset Bit Position 0x078 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 784: Iadc_Scanfifocfg - Scan Fifo Configuration
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.20 IADC_SCANFIFOCFG - Scan FIFO Configuration Offset Bit Position 0x080 Reset Access Name Name Reset Access Description 31:9 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 785: Iadc_Scanfifodata - Scan Fifo Read Data
Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description VALID8 When 8 entries in the scan FIFO are valid, set the SCANFI- FODVL interrupt and request DMA. SHOWID Show ID Enable ID in output words. ALIGNMENT Alignment Alignment of output data written into FIFO.
Page 786: Iadc_Scanfifostat - Scan Fifo Status
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.22 IADC_SCANFIFOSTAT - Scan FIFO Status Offset Bit Position 0x088 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 787: Iadc_Single - Single Queue Port Selection
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.24 IADC_SINGLE - Single Queue Port Selection Offset Bit Position 0x098 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 788 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description PORTB Port B - Select pin number using PINNEG PORTC Port C - Select pin number using PINNEG PORTD Port D - Select pin number using PINNEG PINNEG Negative Pin Select Pin number for the negative input of the ADC.
Page 789: Iadc_Scanx - Scan Entry
Reference Manual IADC - Incremental Analog to Digital Converter 23.5.25 IADC_SCANx - SCAN Entry Offset Bit Position 0x0A0 Reset Access Name Name Reset Access Description 31:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 790 Reference Manual IADC - Incremental Analog to Digital Converter Name Reset Access Description PORTB Port B - Select pin number using PINNEG PORTC Port C - Select pin number using PINNEG PORTD Port D - Select pin number using PINNEG PINNEG Negative Pin Select Pin number for the negative input of the ADC.
Page 791: Gpio - General Purpose Input/Output
Reference Manual GPIO - General Purpose Input/Output 24. GPIO - General Purpose Input/Output Quick Facts What? The General Purpose Input/Output (GPIO) is used for pin configurations as well as routing for peripher- al pin connections. Why? Easy to use and highly configurable input/output pins are important to fit many communication proto- cols as well as minimizing software control over- head.
Page 792: Features
Reference Manual GPIO - General Purpose Input/Output 24.2 Features • Individual configuration for each pin • Tristate (reset state) • Push-pull • Open-drain • Pull-up resistor • Pull-down resistor • Programable Slewrate Control • EM4 IO pin retention • Output enable •...
Page 793: Functional Description
Reference Manual GPIO - General Purpose Input/Output 24.3 Functional Description An overview of the GPIO module is shown in Figure 24.1 Pin Configuration on page 793. The GPIO pins are grouped into 16-pin ports. Each individual GPIO pin is called Pxn where x indicates the port (A, B, C ...) and n indicates the pin number (0,1,..,15). Fewer than 16 pins may be available on some ports depending on the total number of I/O pins on the package.
Page 794: Pin Configuration
Reference Manual GPIO - General Purpose Input/Output 24.3.1 Pin Configuration In addition to setting the pins as either outputs or inputs, the GPIO_Px_MODEL and GPIO_Px_MODEH registers can be used for more advanced configurations. GPIO_Px_MODEL contains 8 bit fields named MODEn (n=0,1,..7) which control pins 0-7, while GPIO_Px_MODEH contains 8 bit fields named MODEn (n=8,9,..15) which control pins 8-15.
Page 795 Reference Manual GPIO - General Purpose Input/Output the input of a GPIO port. The pull-up, pull-down and glitch filter function can optionally be applied to the input, see Figure 24.2 Tristated Output with Optional Pull-up or Pull-down on page 795. Filter enable Optional Input enable...
Page 796: Alternate Port Control
Reference Manual GPIO - General Purpose Input/Output 24.3.2 Alternate Port Control The Alternate Port Control allows for additional flexibility of port level settings. A user may setup two different port configurations (nor- mal and alternate modes) and select which is applied on a pin by pin bases. For example you may configure half of port A to use the slowest slew rate while the other half uses a faster slew rate.
Page 797: Em4 Wakeup
Reference Manual GPIO - General Purpose Input/Output 24.3.8 EM4 Wakeup It is possible to trigger a wake-up from EM4 using any of the selectable EM4WU GPIO pins. The wake-up request can be triggered through the pins by enabling the corresponding bit in the GPIO_EM4WUEN register. When EM4 wake-up is enabled for the pin, the input filter is enabled during EM4.
Page 798: Interrupt Generation
Reference Manual GPIO - General Purpose Input/Output 24.3.9.4 ETM Trace Connections The device includes ETM trace pins. The trace clock can be enabled by setting the TRACECLKPEN bit-field in GPIO_TRACEROUTEP- EN. The data pin(s) can be enabled individually by setting TRACEDATAxPEN in GPIO_TRACEROUTEPEN. The trace pins are fixed location resources connected to specific pins.
Page 799: Output To Prs
Reference Manual GPIO - General Purpose Input/Output 24.3.10.2 Interrupt Generation on EM4WU Pins In addition to being an EM4 wake source, any of the dedicated EM4WU (EM4 wake-up) signals on PA, PB, PC or PD may be used to generate edge-sensitive interrupts in EM0, EM1, EM2, and EM3. In order to enable an EM4WU pin as an interrupt, set the EM4WUIENn field in the GPIO_IEN register and the EM4WUENn field in the EM4WUEN register.
Page 800 Reference Manual GPIO - General Purpose Input/Output 24.3.12.1 Digital Bus (DBUS) The Digital Bus (DBUS) is an any-to-any switch matrix between peripheral resources and GPIO pins as shown in Figure 24.7 Digital Bus Interconnect on page 800. There are two DBUSes on the EFR32xG23 - one serving ports A and B and the other ports C and D. Not all peripherals have access to both DBUSes.
Page 801 Reference Manual GPIO - General Purpose Input/Output 24.3.12.3 Pin Function Tables This section details the functions and GPIO pins available on the most fully-featured devices in the EFR32xG23 family. Availability of GPIO and signals varies. Refer to the device datasheet for specific peripheral and GPIO availability. Fixed-pin peripheral resources are shown in Table 24.3 GPIO Alternate Function Table on page 801, ABUS routing options are listed in...
Page 802 Reference Manual GPIO - General Purpose Input/Output QFN40 with GPIO Alternate Functions QFN48 Package QFN40 Package HFCLKOUT Pack- GPIO.EM4WU6 PC00 LCD.SEG0 PC01 LCD.SEG1 PC02 LCD.SEG2 PC03 LCD.SEG3 PC04 LCD.SEG4 GPIO.EM4WU7 PC05 LCD.SEG5 LCD.SEG6 PC06 GPIO.THMSW_EN GPIO.EM4WU8 PC07 GPIO.THMSW_EN LCD.SEG7 PC08 LCD.SEG18 GPIO.THMSW_EN PC09...
Page 803 Reference Manual GPIO - General Purpose Input/Output Table 24.4. ABUS Routing Table Peripheral Signal EVEN EVEN EVEN EVEN ACMP0 ana_neg ana_pos ACMP1 ana_neg ana_pos IADC0 ana_neg ana_pos VDAC0 ch0_abus_out ch1_abus_out silabs.com | Building a more connected world. Rev. 1.0 | 803...
Page 804 Reference Manual GPIO - General Purpose Input/Output Table 24.5. DBUS Routing Table Peripheral.Resource PORT ACMP0.DIGOUT Available Available Available Available ACMP1.DIGOUT Available Available Available Available CMU.CLKIN0 Available Available CMU.CLKOUT0 Available Available CMU.CLKOUT1 Available Available CMU.CLKOUT2 Available Available EUSART0.CS Available Available EUSART0.CTS Available Available EUSART0.RTS...
Page 805 Reference Manual GPIO - General Purpose Input/Output Peripheral.Resource PORT KEYSCAN.COL_OUT_2 Available Available Available Available KEYSCAN.COL_OUT_3 Available Available Available Available KEYSCAN.COL_OUT_4 Available Available Available Available KEYSCAN.COL_OUT_5 Available Available Available Available KEYSCAN.COL_OUT_6 Available Available Available Available KEYSCAN.COL_OUT_7 Available Available Available Available KEYSCAN.ROW_SENSE_0 Available Available KEYSCAN.ROW_SENSE_1...
Page 806 Reference Manual GPIO - General Purpose Input/Output Peripheral.Resource PORT MODEM.ANT_RR3 Available Available MODEM.ANT_RR4 Available Available MODEM.ANT_RR5 Available Available MODEM.ANT_SW_EN Available Available MODEM.ANT_SW_US Available Available MODEM.ANT_TRIG Available Available MODEM.ANT_TRIG_STOP Available Available MODEM.DCLK Available Available MODEM.DIN Available Available MODEM.DOUT Available Available PCNT0.S0IN Available Available PCNT0.S1IN...
Page 807: Synchronization
Reference Manual GPIO - General Purpose Input/Output Peripheral.Resource PORT TIMER1.CC2 Available Available Available Available TIMER1.CDTI0 Available Available Available Available TIMER1.CDTI1 Available Available Available Available TIMER1.CDTI2 Available Available Available Available TIMER2.CC0 Available Available TIMER2.CC1 Available Available TIMER2.CC2 Available Available TIMER2.CDTI0 Available Available TIMER2.CDTI1 Available...
Page 808: Gpio Register Map
Reference Manual GPIO - General Purpose Input/Output 24.5 GPIO Register Map The offset register address is relative to the registers base address. Offset Name Type Description 0x000 GPIO_IPVERSION Main 0x030 GPIO_PORTA_CTRL Port Control 0x034 GPIO_PORTA_MODEL Mode Low 0x03C GPIO_PORTA_MODEH Mode High 0x040 GPIO_PORTA_DOUT Data Out...
Page 809 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x444 GPIO_TRACEROUTEPEN Trace Route Pin Enable 0x460 GPIO_LCDSEG LCD Segment Enable 0x470 GPIO_LCDCOM LCD Common Enable 0x480 GPIO_ACMP0_ROUTEEN ACMP0 Pin Enable 0x484 GPIO_ACMP0_ACMPOUT- ACMPOUT Port/Pin Select ROUTE 0x48C GPIO_ACMP1_ROUTEEN ACMP1 Pin Enable 0x490 GPIO_ACMP1_ACMPOUT-...
Page 810 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x530 GPIO_FRC_DOUTROUTE DOUT Port/Pin Select 0x538 GPIO_I2C0_ROUTEEN I2C0 Pin Enable 0x53C GPIO_I2C0_SCLROUTE SCL Port/Pin Select 0x540 GPIO_I2C0_SDAROUTE SDA Port/Pin Select 0x548 GPIO_I2C1_ROUTEEN I2C1 Pin Enable 0x54C GPIO_I2C1_SCLROUTE SCL Port/Pin Select 0x550 GPIO_I2C1_SDAROUTE SDA Port/Pin Select...
Page 811 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x5A8 GPIO_LESENSE_CH3OUT- CH3OUT Port/Pin Select ROUTE 0x5AC GPIO_LESENSE_CH4OUT- CH4OUT Port/Pin Select ROUTE 0x5B0 GPIO_LESENSE_CH5OUT- CH5OUT Port/Pin Select ROUTE 0x5B4 GPIO_LESENSE_CH6OUT- CH6OUT Port/Pin Select ROUTE 0x5B8 GPIO_LESENSE_CH7OUT- CH7OUT Port/Pin Select ROUTE 0x5BC GPIO_LESENSE_CH8OUT-...
Page 812 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x614 GPIO_MO- ANTRR5 Port/Pin Select DEM_ANTRR5ROUTE 0x618 GPIO_MODEM_ANTSWEN- ANTSWEN Port/Pin Select ROUTE 0x61C GPIO_MODEM_ANTSWUS- ANTSWUS Port/Pin Select ROUTE 0x620 GPIO_MODEM_ANTTRIG- ANTTRIG Port/Pin Select ROUTE 0x624 GPIO_MODEM_ANTTRIGSTOP- ANTTRIGSTOP Port/Pin Select ROUTE 0x628 GPIO_MODEM_DCLKROUTE...
Page 813 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x708 GPIO_TIMER0_CDTI0ROUTE CDTI0 Port/Pin Select 0x70C GPIO_TIMER0_CDTI1ROUTE CDTI1 Port/Pin Select 0x710 GPIO_TIMER0_CDTI2ROUTE CDTI2 Port/Pin Select 0x718 GPIO_TIMER1_ROUTEEN TIMER1 Pin Enable 0x71C GPIO_TIMER1_CC0ROUTE CC0 Port/Pin Select 0x720 GPIO_TIMER1_CC1ROUTE CC1 Port/Pin Select 0x724 GPIO_TIMER1_CC2ROUTE CC2 Port/Pin Select...
Page 814 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x7B0 GPIO_USART0_TXROUTE TX Port/Pin Select 0x1000 GPIO_IPVERSION_SET Main 0x1030 GPIO_PORTA_CTRL_SET Port Control 0x1034 GPIO_PORTA_MODEL_SET Mode Low 0x103C GPIO_PORTA_MODEH_SET Mode High 0x1040 GPIO_PORTA_DOUT_SET Data Out 0x1044 GPIO_PORTA_DIN_SET Data in 0x1060 GPIO_PORTB_CTRL_SET Port Control 0x1064...
Page 815 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x1460 GPIO_LCDSEG_SET LCD Segment Enable 0x1470 GPIO_LCDCOM_SET LCD Common Enable 0x1480 GPIO_ACMP0_ROUTEEN_SET ACMP0 Pin Enable 0x1484 GPIO_ACMP0_ACMPOUT- ACMPOUT Port/Pin Select ROUTE_SET 0x148C GPIO_ACMP1_ROUTEEN_SET ACMP1 Pin Enable 0x1490 GPIO_ACMP1_ACMPOUT- ACMPOUT Port/Pin Select ROUTE_SET 0x1498 GPIO_CMU_ROUTEEN_SET...
Page 816 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x1504 GPIO_EUSART2_ROU- EUSART2 Pin Enable TEEN_SET 0x1508 GPIO_EU- CS Port/Pin Select SART2_CSROUTE_SET 0x150C GPIO_EU- CTS Port/Pin Select SART2_CTSROUTE_SET 0x1510 GPIO_EU- RTS Port/Pin Select SART2_RTSROUTE_SET 0x1514 GPIO_EU- RX Port/Pin Select SART2_RXROUTE_SET 0x1518 GPIO_EU-...
Page 817 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x157C GPIO_KEYSCAN_ROW- ROWSENSE0 Port/Pin Select SENSE0ROUTE_SET 0x1580 GPIO_KEYSCAN_ROW- ROWSENSE1 Port/Pin Select SENSE1ROUTE_SET 0x1584 GPIO_KEYSCAN_ROW- ROWSENSE2 Port/Pin Select SENSE2ROUTE_SET 0x1588 GPIO_KEYSCAN_ROW- ROWSENSE3 Port/Pin Select SENSE3ROUTE_SET 0x158C GPIO_KEYSCAN_ROW- ROWSENSE4 Port/Pin Select SENSE4ROUTE_SET 0x1590 GPIO_KEYSCAN_ROW-...
Page 818 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x15E0 GPIO_LETIMER_ROU- LETIMER Pin Enable TEEN_SET 0x15E4 GPIO_LETIM- OUT0 Port/Pin Select ER_OUT0ROUTE_SET 0x15E8 GPIO_LETIM- OUT1 Port/Pin Select ER_OUT1ROUTE_SET 0x15F0 GPIO_MODEM_ROUTEEN_SET MODEM Pin Enable 0x15F4 GPIO_MO- ANT0 Port/Pin Select DEM_ANT0ROUTE_SET 0x15F8 GPIO_MO- ANT1 Port/Pin Select...
Page 819 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x1650 GPIO_PRS0_ASYNCH1ROUTE ASYNCH1 Port/Pin Select _SET 0x1654 GPIO_PRS0_ASYNCH2ROUTE ASYNCH2 Port/Pin Select _SET 0x1658 GPIO_PRS0_ASYNCH3ROUTE ASYNCH3 Port/Pin Select _SET 0x165C GPIO_PRS0_ASYNCH4ROUTE ASYNCH4 Port/Pin Select _SET 0x1660 GPIO_PRS0_ASYNCH5ROUTE ASYNCH5 Port/Pin Select _SET 0x1664 GPIO_PRS0_ASYNCH6ROUTE...
Page 820 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x171C GPIO_TIM- CC0 Port/Pin Select ER1_CC0ROUTE_SET 0x1720 GPIO_TIM- CC1 Port/Pin Select ER1_CC1ROUTE_SET 0x1724 GPIO_TIM- CC2 Port/Pin Select ER1_CC2ROUTE_SET 0x1728 GPIO_TIM- CDTI0 Port/Pin Select ER1_CDTI0ROUTE_SET 0x172C GPIO_TIM- CDTI1 Port/Pin Select ER1_CDTI1ROUTE_SET 0x1730 GPIO_TIM-...
Page 821 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x1788 GPIO_TIM- CDTI0 Port/Pin Select ER4_CDTI0ROUTE_SET 0x178C GPIO_TIM- CDTI1 Port/Pin Select ER4_CDTI1ROUTE_SET 0x1790 GPIO_TIM- CDTI2 Port/Pin Select ER4_CDTI2ROUTE_SET 0x1798 GPIO_USART0_ROU- USART0 Pin Enable TEEN_SET 0x179C GPIO_USART0_CSROUTE_SE CS Port/Pin Select 0x17A0 GPIO_USART0_CTSROUTE_S CTS Port/Pin Select...
Page 822 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x2324 GPIO_BBUSALLOC_CLR B Bus Allocation 0x2328 GPIO_CDBUSALLOC_CLR CD Bus Allocation 0x2400 GPIO_EXTIPSELL_CLR External Interrupt Port Select Low 0x2404 GPIO_EXTIPSELH_CLR External Interrupt Port Select High 0x2408 GPIO_EXTIPINSELL_CLR External Interrupt Pin Select Low 0x240C GPIO_EXTIPINSELH_CLR External Interrupt Pin Select High 0x2410...
Page 823 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x24D8 GPIO_EU- SCLK Port/Pin Select SART0_SCLKROUTE_CLR 0x24DC GPIO_EU- TX Port/Pin Select SART0_TXROUTE_CLR 0x24E4 GPIO_EUSART1_ROU- EUSART1 Pin Enable TEEN_CLR 0x24E8 GPIO_EU- CS Port/Pin Select SART1_CSROUTE_CLR 0x24EC GPIO_EU- CTS Port/Pin Select SART1_CTSROUTE_CLR 0x24F0 GPIO_EU-...
Page 824 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x2558 GPIO_KEYSCAN_ROU- KEYSCAN Pin Enable TEEN_CLR 0x255C GPIO_KEYSCAN_COL- COLOUT0 Port/Pin Select OUT0ROUTE_CLR 0x2560 GPIO_KEYSCAN_COL- COLOUT1 Port/Pin Select OUT1ROUTE_CLR 0x2564 GPIO_KEYSCAN_COL- COLOUT2 Port/Pin Select OUT2ROUTE_CLR 0x2568 GPIO_KEYSCAN_COL- COLOUT3 Port/Pin Select OUT3ROUTE_CLR 0x256C GPIO_KEYSCAN_COL- COLOUT4 Port/Pin Select...
Page 825 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x25B8 GPIO_LESENSE_CH7OUT- CH7OUT Port/Pin Select ROUTE_CLR 0x25BC GPIO_LESENSE_CH8OUT- CH8OUT Port/Pin Select ROUTE_CLR 0x25C0 GPIO_LESENSE_CH9OUT- CH9OUT Port/Pin Select ROUTE_CLR 0x25C4 GPIO_LESENSE_CH10OUT- CH10OUT Port/Pin Select ROUTE_CLR 0x25C8 GPIO_LESENSE_CH11OUT- CH11OUT Port/Pin Select ROUTE_CLR 0x25CC GPIO_LESENSE_CH12OUT- CH12OUT Port/Pin Select...
Page 826 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x2620 GPIO_MODEM_ANTTRIG- ANTTRIG Port/Pin Select ROUTE_CLR 0x2624 GPIO_MODEM_ANTTRIGSTOP- ANTTRIGSTOP Port/Pin Select ROUTE_CLR 0x2628 GPIO_MO- DCLK Port/Pin Select DEM_DCLKROUTE_CLR 0x262C GPIO_MODEM_DIN- DIN Port/Pin Select ROUTE_CLR 0x2630 GPIO_MODEM_DOUT- DOUT Port/Pin Select ROUTE_CLR 0x263C GPIO_PCNT0_S0IN- S0IN Port/Pin Select...
Page 827 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x26F0 GPIO_SYXO0_BUFOUTREQI- BUFOUTREQINASYNC Port/Pin Select NASYNCROUTE_CLR 0x26F8 GPIO_TIMER0_ROUTEEN_CLR TIMER0 Pin Enable 0x26FC GPIO_TIM- CC0 Port/Pin Select ER0_CC0ROUTE_CLR 0x2700 GPIO_TIM- CC1 Port/Pin Select ER0_CC1ROUTE_CLR 0x2704 GPIO_TIM- CC2 Port/Pin Select ER0_CC2ROUTE_CLR 0x2708 GPIO_TIM- CDTI0 Port/Pin Select...
Page 828 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x2764 GPIO_TIM- CC2 Port/Pin Select ER3_CC2ROUTE_CLR 0x2768 GPIO_TIM- CDTI0 Port/Pin Select ER3_CDTI0ROUTE_CLR 0x276C GPIO_TIM- CDTI1 Port/Pin Select ER3_CDTI1ROUTE_CLR 0x2770 GPIO_TIM- CDTI2 Port/Pin Select ER3_CDTI2ROUTE_CLR 0x2778 GPIO_TIMER4_ROUTEEN_CLR TIMER4 Pin Enable 0x277C GPIO_TIM- CC0 Port/Pin Select ER4_CC0ROUTE_CLR...
Page 829 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x3090 GPIO_PORTC_CTRL_TGL Port Control 0x3094 GPIO_PORTC_MODEL_TGL Mode Low 0x309C GPIO_PORTC_MODEH_TGL Mode High 0x30A0 GPIO_PORTC_DOUT_TGL Data Out 0x30A4 GPIO_PORTC_DIN_TGL Data in 0x30C0 GPIO_PORTD_CTRL_TGL Port Control 0x30C4 GPIO_PORTD_MODEL_TGL Mode Low 0x30D0 GPIO_PORTD_DOUT_TGL Data Out 0x30D4 GPIO_PORTD_DIN_TGL Data in...
Page 830 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x34A4 GPIO_CMU_CLKOUT1ROUTE_ CLKOUT1 Port/Pin Select 0x34A8 GPIO_CMU_CLKOUT2ROUTE_ CLKOUT2 Port/Pin Select 0x34C4 GPIO_EUSART0_ROU- EUSART0 Pin Enable TEEN_TGL 0x34C8 GPIO_EU- CS Port/Pin Select SART0_CSROUTE_TGL 0x34CC GPIO_EU- CTS Port/Pin Select SART0_CTSROUTE_TGL 0x34D0 GPIO_EU- RTS Port/Pin Select SART0_RTSROUTE_TGL 0x34D4 GPIO_EU-...
Page 831 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x3528 GPIO_FRC_DCLKROUTE_TGL DCLK Port/Pin Select 0x352C GPIO_FRC_DFRAME- DFRAME Port/Pin Select ROUTE_TGL 0x3530 GPIO_FRC_DOUTROUTE_TGL DOUT Port/Pin Select 0x3538 GPIO_I2C0_ROUTEEN_TGL I2C0 Pin Enable 0x353C GPIO_I2C0_SCLROUTE_TGL SCL Port/Pin Select 0x3540 GPIO_I2C0_SDAROUTE_TGL SDA Port/Pin Select 0x3548 GPIO_I2C1_ROUTEEN_TGL I2C1 Pin Enable...
Page 832 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x35A0 GPIO_LESENSE_CH1OUT- CH1OUT Port/Pin Select ROUTE_TGL 0x35A4 GPIO_LESENSE_CH2OUT- CH2OUT Port/Pin Select ROUTE_TGL 0x35A8 GPIO_LESENSE_CH3OUT- CH3OUT Port/Pin Select ROUTE_TGL 0x35AC GPIO_LESENSE_CH4OUT- CH4OUT Port/Pin Select ROUTE_TGL 0x35B0 GPIO_LESENSE_CH5OUT- CH5OUT Port/Pin Select ROUTE_TGL 0x35B4 GPIO_LESENSE_CH6OUT-...
Page 833 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x3608 GPIO_MO- ANTRR2 Port/Pin Select DEM_ANTRR2ROUTE_TGL 0x360C GPIO_MO- ANTRR3 Port/Pin Select DEM_ANTRR3ROUTE_TGL 0x3610 GPIO_MO- ANTRR4 Port/Pin Select DEM_ANTRR4ROUTE_TGL 0x3614 GPIO_MO- ANTRR5 Port/Pin Select DEM_ANTRR5ROUTE_TGL 0x3618 GPIO_MODEM_ANTSWEN- ANTSWEN Port/Pin Select ROUTE_TGL 0x361C GPIO_MODEM_ANTSWUS- ANTSWUS Port/Pin Select...
Page 834 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x3674 GPIO_PRS0_ASYNCH10ROUT ASYNCH10 Port/Pin Select E_TGL 0x3678 GPIO_PRS0_ASYNCH11ROUT ASYNCH11 Port/Pin Select E_TGL 0x367C GPIO_PRS0_SYNCH0ROUTE_ SYNCH0 Port/Pin Select 0x3680 GPIO_PRS0_SYNCH1ROUTE_ SYNCH1 Port/Pin Select 0x3684 GPIO_PRS0_SYNCH2ROUTE_ SYNCH2 Port/Pin Select 0x3688 GPIO_PRS0_SYNCH3ROUTE_ SYNCH3 Port/Pin Select 0x36F0 GPIO_SYXO0_BUFOUTREQI-...
Page 835 Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x3744 GPIO_TIM- CC2 Port/Pin Select ER2_CC2ROUTE_TGL 0x3748 GPIO_TIM- CDTI0 Port/Pin Select ER2_CDTI0ROUTE_TGL 0x374C GPIO_TIM- CDTI1 Port/Pin Select ER2_CDTI1ROUTE_TGL 0x3750 GPIO_TIM- CDTI2 Port/Pin Select ER2_CDTI2ROUTE_TGL 0x3758 GPIO_TIMER3_ROUTEEN_TGL TIMER3 Pin Enable 0x375C GPIO_TIM- CC0 Port/Pin Select ER3_CC0ROUTE_TGL...
Page 836: Gpio Register Description
Reference Manual GPIO - General Purpose Input/Output Offset Name Type Description 0x37B0 GPIO_USART0_TXROUTE_TGL TX Port/Pin Select 24.6 GPIO Register Description 24.6.1 GPIO_IPVERSION - Main Offset Bit Position 0x000 Reset Access Name Name Reset Access Description 31:0 IPVERSION ip version id IPVERSION ID silabs.com | Building a more connected world.
Page 837: Gpio_Porta_Ctrl - Port Control
Reference Manual GPIO - General Purpose Input/Output 24.6.2 GPIO_PORTA_CTRL - Port Control Offset Bit Position 0x030 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 838: Gpio_Porta_Model - Mode Low
Reference Manual GPIO - General Purpose Input/Output 24.6.3 GPIO_PORTA_MODEL - Mode Low Offset Bit Position 0x034 Reset Access Name Name Reset Access Description 31:28 MODE7 MODE n MODE n Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled.
Page 839 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter. WIREDANDPULLUP Open-drain output with pullup. WIREDANDPULLUPFIL- Open-drain output with filter and pullup.
Page 840 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set. INPUTPULL Input enabled. DOUT determines pull direction. INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output.
Page 841 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup. FILTER 11:8 MODE2 MODE n MODE n Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled.
Page 842 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDPULLUPFIL- Open-drain output with filter and pullup. WIREDANDALT Open-drain output using alternate control. WIREDANDALTFILTER Open-drain output using alternate control with filter. WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup.
Page 843: Gpio_Porta_Modeh - Mode High
Reference Manual GPIO - General Purpose Input/Output 24.6.4 GPIO_PORTA_MODEH - Mode High Offset Bit Position 0x03C Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 844 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter.
Page 845: Gpio_Porta_Dout - Data Out
Reference Manual GPIO - General Purpose Input/Output 24.6.5 GPIO_PORTA_DOUT - Data Out Offset Bit Position 0x040 Reset Access Name Name Reset Access Description 31:11 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 846: Gpio_Portb_Ctrl - Port Control
Reference Manual GPIO - General Purpose Input/Output 24.6.7 GPIO_PORTB_CTRL - Port Control Offset Bit Position 0x060 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 847: Gpio_Portb_Model - Mode Low
Reference Manual GPIO - General Purpose Input/Output 24.6.8 GPIO_PORTB_MODEL - Mode Low Offset Bit Position 0x064 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 848 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter.
Page 849 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set. INPUTPULL Input enabled. DOUT determines pull direction. INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output.
Page 850 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup. FILTER MODE1 MODE n MODE n Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled.
Page 851: Gpio_Portb_Dout - Data Out
Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDPULLUP Open-drain output with pullup. WIREDANDPULLUPFIL- Open-drain output with filter and pullup. WIREDANDALT Open-drain output using alternate control. WIREDANDALTFILTER Open-drain output using alternate control with filter. WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup.
Page 852: Gpio_Portc_Ctrl - Port Control
Reference Manual GPIO - General Purpose Input/Output 24.6.11 GPIO_PORTC_CTRL - Port Control Offset Bit Position 0x090 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 853: Gpio_Portc_Model - Mode Low
Reference Manual GPIO - General Purpose Input/Output 24.6.12 GPIO_PORTC_MODEL - Mode Low Offset Bit Position 0x094 Reset Access Name Name Reset Access Description 31:28 MODE7 MODE n MODE n Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled.
Page 854 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter. WIREDANDPULLUP Open-drain output with pullup. WIREDANDPULLUPFIL- Open-drain output with filter and pullup.
Page 855 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set. INPUTPULL Input enabled. DOUT determines pull direction. INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output.
Page 856 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup. FILTER 11:8 MODE2 MODE n MODE n Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled.
Page 857 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDPULLUPFIL- Open-drain output with filter and pullup. WIREDANDALT Open-drain output using alternate control. WIREDANDALTFILTER Open-drain output using alternate control with filter. WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup.
Page 858: Gpio_Portc_Modeh - Mode High
Reference Manual GPIO - General Purpose Input/Output 24.6.13 GPIO_PORTC_MODEH - Mode High Offset Bit Position 0x09C Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 859: Gpio_Portc_Dout - Data Out
Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter.
Page 860: Gpio_Portc_Din - Data In
Reference Manual GPIO - General Purpose Input/Output 24.6.15 GPIO_PORTC_DIN - Data in Offset Bit Position 0x0A4 Reset Access Name Name Reset Access Description 31:10 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 861: Gpio_Portd_Ctrl - Port Control
Reference Manual GPIO - General Purpose Input/Output 24.6.16 GPIO_PORTD_CTRL - Port Control Offset Bit Position 0x0C0 Reset Access Name Name Reset Access Description 31:29 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 862: Gpio_Portd_Model - Mode Low
Reference Manual GPIO - General Purpose Input/Output 24.6.17 GPIO_PORTD_MODEL - Mode Low Offset Bit Position 0x0C4 Reset Access Name Name Reset Access Description 31:24 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 863 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output. PUSHPULLALT Push-pull using alternate control. WIREDOR Wired-or output. WIREDORPULLDOWN Wired-or output with pull-down. WIREDAND Open-drain output. WIREDANDFILTER Open-drain output with filter.
Page 864 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled. Filter if DOUT is set. INPUTPULL Input enabled. DOUT determines pull direction. INPUTPULLFILTER Input enabled with filter. DOUT determines pull direction. PUSHPULL Push-pull output.
Page 865: Gpio_Portd_Dout - Data Out
Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description WIREDANDALTPULLUP Open-drain output using alternate control with pullup. WIREDANDALTPULLUP- Open-drain output using alternate control with filter and pullup. FILTER MODE0 MODE n MODE n Value Mode Description DISABLED Input disabled. Pullup if DOUT is set. INPUT Input enabled.
Page 866: Gpio_Portd_Din - Data In
Reference Manual GPIO - General Purpose Input/Output 24.6.19 GPIO_PORTD_DIN - Data in Offset Bit Position 0x0D4 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 867: Gpio_Gpiolockstatus - Lock Status
Reference Manual GPIO - General Purpose Input/Output 24.6.21 GPIO_GPIOLOCKSTATUS - Lock Status Offset Bit Position 0x310 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 868: Gpio_Abusalloc - A Bus Allocation
Reference Manual GPIO - General Purpose Input/Output 24.6.22 GPIO_ABUSALLOC - A Bus Allocation Offset Bit Position 0x320 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 869 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ACMP1 The bus is allocated to ACMP1 VDAC0CH1 The bus is allocated to VDAC0 CH1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 870: Gpio_Bbusalloc - B Bus Allocation
Reference Manual GPIO - General Purpose Input/Output 24.6.23 GPIO_BBUSALLOC - B Bus Allocation Offset Bit Position 0x324 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 871 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ACMP1 The bus is allocated to ACMP1 VDAC0CH1 The bus is allocated to VDAC0 CH1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 872: Gpio_Cdbusalloc - Cd Bus Allocation
Reference Manual GPIO - General Purpose Input/Output 24.6.24 GPIO_CDBUSALLOC - CD Bus Allocation Offset Bit Position 0x328 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 873 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ACMP1 The bus is allocated to ACMP1 VDAC0CH1 The bus is allocated to VDAC0 CH1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 874: Gpio_Extipsell - External Interrupt Port Select Low
Reference Manual GPIO - General Purpose Input/Output 24.6.25 GPIO_EXTIPSELL - External Interrupt Port Select Low Offset Bit Position 0x400 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 875 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 19:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 17:16 EXTIPSEL4 External Interrupt Port Select Port select for external interrupt 4 (EXTI4) Value Mode...
Page 876 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions EXTIPSEL0 External Interrupt Port Select Port select for external interrupt 0 (EXTI0) Value Mode...
Page 877: Gpio_Extipselh - External Interrupt Port Select High
Reference Manual GPIO - General Purpose Input/Output 24.6.26 GPIO_EXTIPSELH - External Interrupt Port Select High Offset Bit Position 0x404 Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 878 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions EXTIPSEL0 External Interrupt Port Select Port select for external interrupt 0+8 Value Mode...
Page 879: Gpio_Extipinsell - External Interrupt Pin Select Low
Reference Manual GPIO - General Purpose Input/Output 24.6.27 GPIO_EXTIPINSELL - External Interrupt Pin Select Low Offset Bit Position 0x408 Reset Access Name Name Reset Access Description 31:30 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 880 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description 19:18 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions 17:16 EXTIPINSEL4 External Interrupt Pin select OFFSET select for External Interrupt 4 (EXTI4) Value Mode...
Page 881 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions EXTIPINSEL0 External Interrupt Pin select OFFSET select for External Interrupt 0 (EXTI0) Value Mode...
Page 882: Gpio_Extipinselh - External Interrupt Pin Select High
Reference Manual GPIO - General Purpose Input/Output 24.6.28 GPIO_EXTIPINSELH - External Interrupt Pin Select High Offset Bit Position 0x40C Reset Access Name Name Reset Access Description 31:14 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 883: Gpio_Extirise - External Interrupt Rising Edge Trigger
Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated. More information in 1.2 Conventions EXTIPINSEL0 External Interrupt Pin select OFFSET select for External Interrupt {b+8} (EXTI{b+8}) Value Mode...
Page 884: Gpio_Extifall - External Interrupt Falling Edge Trigger
Reference Manual GPIO - General Purpose Input/Output 24.6.30 GPIO_EXTIFALL - External Interrupt Falling Edge Trigger Offset Bit Position 0x414 Reset Access Name Name Reset Access Description 31:12 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 885: Gpio_If - Interrupt Flag
Reference Manual GPIO - General Purpose Input/Output 24.6.31 GPIO_IF - Interrupt Flag Offset Bit Position 0x420 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 886 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description External Pin interrupt flag silabs.com | Building a more connected world. Rev. 1.0 | 886...
Page 887: Gpio_Ien - Interrupt Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.32 GPIO_IEN - Interrupt Enable Offset Bit Position 0x424 Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 888 Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description EXTIEN11 External Pin Enable External Pin interrupt enable EXTIEN10 External Pin Enable External Pin interrupt enable EXTIEN9 External Pin Enable External Pin interrupt enable EXTIEN8 External Pin Enable External Pin interrupt enable EXTIEN7 External Pin Enable External Pin interrupt enable...
Page 889: Gpio_Em4Wuen - Em4 Wakeup Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.33 GPIO_EM4WUEN - EM4 Wakeup Enable Offset Bit Position 0x42C Reset Access Name Name Reset Access Description 31:28 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 890: Gpio_Dbgroutepen - Debugger Route Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.35 GPIO_DBGROUTEPEN - Debugger Route Pin Enable Offset Bit Position 0x440 Reset Access Name Name Reset Access Description 31:4 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 891: Gpio_Traceroutepen - Trace Route Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.36 GPIO_TRACEROUTEPEN - Trace Route Pin Enable Offset Bit Position 0x444 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 892: Gpio_Lcdseg - Lcd Segment Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.37 GPIO_LCDSEG - LCD Segment Enable Offset Bit Position 0x460 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 893: Gpio_Acmp0_Routeen - Acmp0 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.39 GPIO_ACMP0_ROUTEEN - ACMP0 Pin Enable Offset Bit Position 0x480 Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 894: Gpio_Acmp1_Routeen - Acmp1 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.41 GPIO_ACMP1_ROUTEEN - ACMP1 Pin Enable Offset Bit Position 0x48C Reset Access Name Name Reset Access Description 31:1 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 895: Gpio_Cmu_Routeen - Cmu Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.43 GPIO_CMU_ROUTEEN - CMU Pin Enable Offset Bit Position 0x498 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 896: Gpio_Cmu_Clkout0Route - Clkout0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.45 GPIO_CMU_CLKOUT0ROUTE - CLKOUT0 Port/Pin Select Offset Bit Position 0x4A0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 897: Gpio_Cmu_Clkout2Route - Clkout2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.47 GPIO_CMU_CLKOUT2ROUTE - CLKOUT2 Port/Pin Select Offset Bit Position 0x4A8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 898: Gpio_Eusart0_Routeen - Eusart0 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.48 GPIO_EUSART0_ROUTEEN - EUSART0 Pin Enable Offset Bit Position 0x4C4 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 899: Gpio_Eusart0_Csroute - Cs Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.49 GPIO_EUSART0_CSROUTE - CS Port/Pin Select Offset Bit Position 0x4C8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 900: Gpio_Eusart0_Rtsroute - Rts Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.51 GPIO_EUSART0_RTSROUTE - RTS Port/Pin Select Offset Bit Position 0x4D0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 901: Gpio_Eusart0_Sclkroute - Sclk Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.53 GPIO_EUSART0_SCLKROUTE - SCLK Port/Pin Select Offset Bit Position 0x4D8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 902: Gpio_Eusart1_Routeen - Eusart1 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.55 GPIO_EUSART1_ROUTEEN - EUSART1 Pin Enable Offset Bit Position 0x4E4 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 903: Gpio_Eusart1_Csroute - Cs Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.56 GPIO_EUSART1_CSROUTE - CS Port/Pin Select Offset Bit Position 0x4E8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 904: Gpio_Eusart1_Rtsroute - Rts Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.58 GPIO_EUSART1_RTSROUTE - RTS Port/Pin Select Offset Bit Position 0x4F0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 905: Gpio_Eusart1_Sclkroute - Sclk Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.60 GPIO_EUSART1_SCLKROUTE - SCLK Port/Pin Select Offset Bit Position 0x4F8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 906: Gpio_Eusart2_Routeen - Eusart2 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.62 GPIO_EUSART2_ROUTEEN - EUSART2 Pin Enable Offset Bit Position 0x504 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 907: Gpio_Eusart2_Csroute - Cs Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.63 GPIO_EUSART2_CSROUTE - CS Port/Pin Select Offset Bit Position 0x508 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 908: Gpio_Eusart2_Rtsroute - Rts Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.65 GPIO_EUSART2_RTSROUTE - RTS Port/Pin Select Offset Bit Position 0x510 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 909: Gpio_Eusart2_Sclkroute - Sclk Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.67 GPIO_EUSART2_SCLKROUTE - SCLK Port/Pin Select Offset Bit Position 0x518 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 910: Gpio_Frc_Routeen - Frc Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.69 GPIO_FRC_ROUTEEN - FRC Pin Enable Offset Bit Position 0x524 Reset Access Name Name Reset Access Description 31:3 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 911: Gpio_Frc_Dframeroute - Dframe Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.71 GPIO_FRC_DFRAMEROUTE - DFRAME Port/Pin Select Offset Bit Position 0x52C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 912: Gpio_I2C0_Routeen - I2C0 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.73 GPIO_I2C0_ROUTEEN - I2C0 Pin Enable Offset Bit Position 0x538 Reset Access Name Name Reset Access Description 31:2 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 913: Gpio_I2C0_Sdaroute - Sda Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.75 GPIO_I2C0_SDAROUTE - SDA Port/Pin Select Offset Bit Position 0x540 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 914: Gpio_I2C1_Sclroute - Scl Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.77 GPIO_I2C1_SCLROUTE - SCL Port/Pin Select Offset Bit Position 0x54C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 915: Gpio_Keyscan_Routeen - Keyscan Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.79 GPIO_KEYSCAN_ROUTEEN - KEYSCAN Pin Enable Offset Bit Position 0x558 Reset Access Name Name Reset Access Description 31:8 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 916: Gpio_Keyscan_Colout0Route - Colout0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.80 GPIO_KEYSCAN_COLOUT0ROUTE - COLOUT0 Port/Pin Select Offset Bit Position 0x55C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 917: Gpio_Keyscan_Colout2Route - Colout2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.82 GPIO_KEYSCAN_COLOUT2ROUTE - COLOUT2 Port/Pin Select Offset Bit Position 0x564 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 918: Gpio_Keyscan_Colout4Route - Colout4 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.84 GPIO_KEYSCAN_COLOUT4ROUTE - COLOUT4 Port/Pin Select Offset Bit Position 0x56C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 919: Gpio_Keyscan_Colout6Route - Colout6 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.86 GPIO_KEYSCAN_COLOUT6ROUTE - COLOUT6 Port/Pin Select Offset Bit Position 0x574 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 920: Gpio_Keyscan_Rowsense0Route - Rowsense0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.88 GPIO_KEYSCAN_ROWSENSE0ROUTE - ROWSENSE0 Port/Pin Select Offset Bit Position 0x57C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 921: Gpio_Keyscan_Rowsense2Route - Rowsense2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.90 GPIO_KEYSCAN_ROWSENSE2ROUTE - ROWSENSE2 Port/Pin Select Offset Bit Position 0x584 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 922: Gpio_Keyscan_Rowsense4Route - Rowsense4 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.92 GPIO_KEYSCAN_ROWSENSE4ROUTE - ROWSENSE4 Port/Pin Select Offset Bit Position 0x58C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 923: Gpio_Lesense_Routeen - Lesense Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.94 GPIO_LESENSE_ROUTEEN - LESENSE Pin Enable Offset Bit Position 0x598 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 924: Gpio_Lesense_Ch0Outroute - Ch0Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description CH3OUT pin enable control bit CH2OUTPEN CH2OUT pin enable control bit CH2OUT pin enable control bit CH1OUTPEN CH1OUT pin enable control bit CH1OUT pin enable control bit CH0OUTPEN CH0OUT pin enable control bit CH0OUT pin enable control bit 24.6.95 GPIO_LESENSE_CH0OUTROUTE - CH0OUT Port/Pin Select Offset...
Page 925: Gpio_Lesense_Ch1Outroute - Ch1Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.96 GPIO_LESENSE_CH1OUTROUTE - CH1OUT Port/Pin Select Offset Bit Position 0x5A0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 926: Gpio_Lesense_Ch3Outroute - Ch3Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.98 GPIO_LESENSE_CH3OUTROUTE - CH3OUT Port/Pin Select Offset Bit Position 0x5A8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 927: Gpio_Lesense_Ch5Outroute - Ch5Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.100 GPIO_LESENSE_CH5OUTROUTE - CH5OUT Port/Pin Select Offset Bit Position 0x5B0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 928: Gpio_Lesense_Ch7Outroute - Ch7Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.102 GPIO_LESENSE_CH7OUTROUTE - CH7OUT Port/Pin Select Offset Bit Position 0x5B8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 929: Gpio_Lesense_Ch9Outroute - Ch9Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.104 GPIO_LESENSE_CH9OUTROUTE - CH9OUT Port/Pin Select Offset Bit Position 0x5C0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 930: Gpio_Lesense_Ch11Outroute - Ch11Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.106 GPIO_LESENSE_CH11OUTROUTE - CH11OUT Port/Pin Select Offset Bit Position 0x5C8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 931: Gpio_Lesense_Ch13Outroute - Ch13Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.108 GPIO_LESENSE_CH13OUTROUTE - CH13OUT Port/Pin Select Offset Bit Position 0x5D0 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 932: Gpio_Lesense_Ch15Outroute - Ch15Out Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.110 GPIO_LESENSE_CH15OUTROUTE - CH15OUT Port/Pin Select Offset Bit Position 0x5D8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 933: Gpio_Letimer_Out0Route - Out0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.112 GPIO_LETIMER_OUT0ROUTE - OUT0 Port/Pin Select Offset Bit Position 0x5E4 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 934: Gpio_Modem_Routeen - Modem Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.114 GPIO_MODEM_ROUTEEN - MODEM Pin Enable Offset Bit Position 0x5F0 Reset Access Name Name Reset Access Description 31:15 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 935: Gpio_Modem_Ant0Route - Ant0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ANTROLLOVERPEN ANTROLLOVER pin enable control bit ANTROLLOVER pin enable control bit ANT1PEN ANT1 pin enable control bit ANT1 pin enable control bit ANT0PEN ANT0 pin enable control bit ANT0 pin enable control bit 24.6.115 GPIO_MODEM_ANT0ROUTE - ANT0 Port/Pin Select Offset Bit Position...
Page 936: Gpio_Modem_Ant1Route - Ant1 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.116 GPIO_MODEM_ANT1ROUTE - ANT1 Port/Pin Select Offset Bit Position 0x5F8 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 937: Gpio_Modem_Antrr0Route - Antrr0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.118 GPIO_MODEM_ANTRR0ROUTE - ANTRR0 Port/Pin Select Offset Bit Position 0x600 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 938: Gpio_Modem_Antrr2Route - Antrr2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.120 GPIO_MODEM_ANTRR2ROUTE - ANTRR2 Port/Pin Select Offset Bit Position 0x608 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 939: Gpio_Modem_Antrr4Route - Antrr4 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.122 GPIO_MODEM_ANTRR4ROUTE - ANTRR4 Port/Pin Select Offset Bit Position 0x610 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 940: Gpio_Modem_Antswenroute - Antswen Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.124 GPIO_MODEM_ANTSWENROUTE - ANTSWEN Port/Pin Select Offset Bit Position 0x618 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 941: Gpio_Modem_Anttrigroute - Anttrig Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.126 GPIO_MODEM_ANTTRIGROUTE - ANTTRIG Port/Pin Select Offset Bit Position 0x620 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 942: Gpio_Modem_Dclkroute - Dclk Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.128 GPIO_MODEM_DCLKROUTE - DCLK Port/Pin Select Offset Bit Position 0x628 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 943: Gpio_Modem_Doutroute - Dout Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.130 GPIO_MODEM_DOUTROUTE - DOUT Port/Pin Select Offset Bit Position 0x630 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 944: Gpio_Pcnt0_S1Inroute - S1In Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.132 GPIO_PCNT0_S1INROUTE - S1IN Port/Pin Select Offset Bit Position 0x640 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 945: Gpio_Prs0_Routeen - Prs0 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.133 GPIO_PRS0_ROUTEEN - PRS0 Pin Enable Offset Bit Position 0x648 Reset Access Name Name Reset Access Description 31:16 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 946: Gpio_Prs0_Asynch0Route - Asynch0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output Name Reset Access Description ASYNCH3 pin enable control bit ASYNCH2PEN ASYNCH2 pin enable control bit ASYNCH2 pin enable control bit ASYNCH1PEN ASYNCH1 pin enable control bit ASYNCH1 pin enable control bit ASYNCH0PEN ASYNCH0 pin enable control bit ASYNCH0 pin enable control bit 24.6.134 GPIO_PRS0_ASYNCH0ROUTE - ASYNCH0 Port/Pin Select Offset...
Page 947: Gpio_Prs0_Asynch2Route - Asynch2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.135 GPIO_PRS0_ASYNCH1ROUTE - ASYNCH1 Port/Pin Select Offset Bit Position 0x650 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 948: Gpio_Prs0_Asynch3Route - Asynch3 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.137 GPIO_PRS0_ASYNCH3ROUTE - ASYNCH3 Port/Pin Select Offset Bit Position 0x658 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 949: Gpio_Prs0_Asynch5Route - Asynch5 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.139 GPIO_PRS0_ASYNCH5ROUTE - ASYNCH5 Port/Pin Select Offset Bit Position 0x660 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 950: Gpio_Prs0_Asynch7Route - Asynch7 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.141 GPIO_PRS0_ASYNCH7ROUTE - ASYNCH7 Port/Pin Select Offset Bit Position 0x668 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 951: Gpio_Prs0_Asynch9Route - Asynch9 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.143 GPIO_PRS0_ASYNCH9ROUTE - ASYNCH9 Port/Pin Select Offset Bit Position 0x670 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 952: Gpio_Prs0_Asynch11Route - Asynch11 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.145 GPIO_PRS0_ASYNCH11ROUTE - ASYNCH11 Port/Pin Select Offset Bit Position 0x678 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 953: Gpio_Prs0_Synch1Route - Synch1 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.147 GPIO_PRS0_SYNCH1ROUTE - SYNCH1 Port/Pin Select Offset Bit Position 0x680 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 954: Gpio_Prs0_Synch3Route - Synch3 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.149 GPIO_PRS0_SYNCH3ROUTE - SYNCH3 Port/Pin Select Offset Bit Position 0x688 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 955: Gpio_Timer0_Routeen - Timer0 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.151 GPIO_TIMER0_ROUTEEN - TIMER0 Pin Enable Offset Bit Position 0x6F8 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 956: Gpio_Timer0_Cc0Route - Cc0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.152 GPIO_TIMER0_CC0ROUTE - CC0 Port/Pin Select Offset Bit Position 0x6FC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 957: Gpio_Timer0_Cc2Route - Cc2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.154 GPIO_TIMER0_CC2ROUTE - CC2 Port/Pin Select Offset Bit Position 0x704 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 958: Gpio_Timer0_Cdti1Route - Cdti1 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.156 GPIO_TIMER0_CDTI1ROUTE - CDTI1 Port/Pin Select Offset Bit Position 0x70C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 959: Gpio_Timer1_Routeen - Timer1 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.158 GPIO_TIMER1_ROUTEEN - TIMER1 Pin Enable Offset Bit Position 0x718 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 960: Gpio_Timer1_Cc0Route - Cc0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.159 GPIO_TIMER1_CC0ROUTE - CC0 Port/Pin Select Offset Bit Position 0x71C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 961: Gpio_Timer1_Cc2Route - Cc2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.161 GPIO_TIMER1_CC2ROUTE - CC2 Port/Pin Select Offset Bit Position 0x724 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 962: Gpio_Timer1_Cdti1Route - Cdti1 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.163 GPIO_TIMER1_CDTI1ROUTE - CDTI1 Port/Pin Select Offset Bit Position 0x72C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 963: Gpio_Timer2_Routeen - Timer2 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.165 GPIO_TIMER2_ROUTEEN - TIMER2 Pin Enable Offset Bit Position 0x738 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 964: Gpio_Timer2_Cc0Route - Cc0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.166 GPIO_TIMER2_CC0ROUTE - CC0 Port/Pin Select Offset Bit Position 0x73C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 965: Gpio_Timer2_Cc2Route - Cc2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.168 GPIO_TIMER2_CC2ROUTE - CC2 Port/Pin Select Offset Bit Position 0x744 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 966: Gpio_Timer2_Cdti1Route - Cdti1 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.170 GPIO_TIMER2_CDTI1ROUTE - CDTI1 Port/Pin Select Offset Bit Position 0x74C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 967: Gpio_Timer3_Routeen - Timer3 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.172 GPIO_TIMER3_ROUTEEN - TIMER3 Pin Enable Offset Bit Position 0x758 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 968: Gpio_Timer3_Cc0Route - Cc0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.173 GPIO_TIMER3_CC0ROUTE - CC0 Port/Pin Select Offset Bit Position 0x75C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 969: Gpio_Timer3_Cc2Route - Cc2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.175 GPIO_TIMER3_CC2ROUTE - CC2 Port/Pin Select Offset Bit Position 0x764 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 970: Gpio_Timer3_Cdti1Route - Cdti1 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.177 GPIO_TIMER3_CDTI1ROUTE - CDTI1 Port/Pin Select Offset Bit Position 0x76C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 971: Gpio_Timer4_Routeen - Timer4 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.179 GPIO_TIMER4_ROUTEEN - TIMER4 Pin Enable Offset Bit Position 0x778 Reset Access Name Name Reset Access Description 31:6 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 972: Gpio_Timer4_Cc0Route - Cc0 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.180 GPIO_TIMER4_CC0ROUTE - CC0 Port/Pin Select Offset Bit Position 0x77C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 973: Gpio_Timer4_Cc2Route - Cc2 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.182 GPIO_TIMER4_CC2ROUTE - CC2 Port/Pin Select Offset Bit Position 0x784 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 974: Gpio_Timer4_Cdti1Route - Cdti1 Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.184 GPIO_TIMER4_CDTI1ROUTE - CDTI1 Port/Pin Select Offset Bit Position 0x78C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 975: Gpio_Usart0_Routeen - Usart0 Pin Enable
Reference Manual GPIO - General Purpose Input/Output 24.6.186 GPIO_USART0_ROUTEEN - USART0 Pin Enable Offset Bit Position 0x798 Reset Access Name Name Reset Access Description 31:5 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 976: Gpio_Usart0_Csroute - Cs Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.187 GPIO_USART0_CSROUTE - CS Port/Pin Select Offset Bit Position 0x79C Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 977: Gpio_Usart0_Rtsroute - Rts Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.189 GPIO_USART0_RTSROUTE - RTS Port/Pin Select Offset Bit Position 0x7A4 Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 978: Gpio_Usart0_Clkroute - Sclk Port/Pin Select
Reference Manual GPIO - General Purpose Input/Output 24.6.191 GPIO_USART0_CLKROUTE - SCLK Port/Pin Select Offset Bit Position 0x7AC Reset Access Name Name Reset Access Description 31:20 Reserved To ensure compatibility with future devices, always write Reserved bits to their reset value, un- less otherwise stated.
Page 979: Ldma - Linked Dma
Reference Manual LDMA - Linked DMA 25. LDMA - Linked DMA Quick Facts What? The LDMA controller can move data without CPU in- tervention, effectively reducing the energy consump- tion for a data transfer. Why? The LDMA can perform data transfers more energy efficiently than the CPU and allows autonomous op- Flash eration in low energy modes.
Page 980: Features
Reference Manual LDMA - Linked DMA 25.1.1 Features • Flexible Source and Destination transfers • Memory-to-memory • Memory-to-peripheral • Peripheral-to-memory • Peripheral-to-peripheral • DMA transfers triggered by peripherals, software, or linked list • Single or multiple data transfers for each peripheral or software request •...
Page 981: Block Diagram
Reference Manual LDMA - Linked DMA 25.2 Block Diagram An overview of the LDMA and the modules it interacts with is shown in Figure 25.1 LDMA Block Diagram on page 981. Cortex Interrupts LDMA Core Error Channel done Channel 0 Peripheral Channel 1 Peripheral...
Page 982: Functional Description
Reference Manual LDMA - Linked DMA 25.3 Functional Description The Linked DMA Controller is highly flexible. It is capable of transferring data between peripherals and memory without involvement from the processor core. This can be used to increase system performance by off-loading the processor from copying large amounts of data or avoiding frequent interrupts to service peripherals needing more data or having available data.
Page 983 Reference Manual LDMA - Linked DMA 25.3.1.3 Block Size The block size defines the amount of data transferred in one arbitration. It consists of one or more DMA transfers. See 25.3.6.1 Arbitra- tion Priority for more details. 25.3.1.4 Transfer Count The descriptor transfer count defines how many DMA transfers to perform.
Page 984 Reference Manual LDMA - Linked DMA 25.3.1.8 Byte Swap Enabling byte swap reverses the endianness of the incoming source data read into the LDMA’s FIFO. Byte swap is only valid for trans- fer sizes of word and half-word. Note that linked structure reads are not byte swapped. B3b7 B3b0 B2b7...
Page 985 Reference Manual LDMA - Linked DMA 25.3.1.9 DMA Size and Source/Destination Increment Programming The DMA channels’ SIZE, SRCINC, and DSTINC bit-fields are programmed to best utilize memory resources. They provide a means for memory packing and unpacking, as well as for matching the size of data being transmitted to or received from an IO peripheral. The following figure shows how 32-bit words of data are read from a memory source into the DMA’s internal transfer FIFO, and then written out to the memory destination.
Page 986 Reference Manual LDMA - Linked DMA Memory Memory source source 0x200 0x200 First read transmit data= First read transmit data= DMA Controller FIFO DMA Controller FIFO destination destination 0x400 0x400 First write transmit data= First write transmit data= size[1:0] = HALF size[1:0] = HALF src_inc[1:0] = WORD src_inc[1:0] = HALF...
Page 987: Channel Configuration
Reference Manual LDMA - Linked DMA 25.3.2 Channel Configuration Each DMA channel has associated configuration and loop counter registers for controlling direction of address increment , arbitration slots, and descriptor looping. 25.3.2.1 Address Increment/Decrement Normally DMA transfers increment the source and destination addresses after each DMA transfer. Each channel is also capable of dec- rementing the source and/or destination addresses after each DMA transfer.
Page 988: Managing Transfer Errors
Reference Manual LDMA - Linked DMA 25.3.4.1 Peripheral Transfer Requests By default peripherals issue a Single Request (SREQ) when any data is present. For peripherals with a data buffer or FIFO this occurs any time the FIFO is not empty. Upon receiving an SREQ the LDMA will perform one DMA transfer and stop till another request is made.
Page 989 Reference Manual LDMA - Linked DMA Table 25.1. Arbitration Slot Order Arbslot order Arbslot1 Arbslot2 Arbslot4 Arbslot8 The top row shows the order at which the arbitration slots are executed. The remaining part of the table shows a more visual interpreta- tion of the arbitration order.
Page 990: Channel Descriptor Data Structure
Reference Manual LDMA - Linked DMA 25.3.6.2 DMA Transfer Arbitration In addition to the inter channel arbitration, software can configure when the controller arbitrates during a DMA transfer. This provides reduced latency to higher priority channels when configuring low priority transfers with more arbitration cycles. The LDMA provides four bits that configure how many DMA transfers occur before it re-arbitrates.
Page 991 Reference Manual LDMA - Linked DMA 25.3.7.1 XFER Descriptor Structure This descriptor defines a typical data transfer which may be a Normal, Link, or Loop transfer. Only this structure type can be written directly into LDMA's registers by the CPU. All descriptors may be linked to. Please refer to the register descriptions for additional information.
Page 992 Reference Manual LDMA - Linked DMA 25.3.7.2 SYNC Descriptor Structure This descriptor defines an intra-channel synchronizing structure. It allows the channel to wait for some external stimulus before continu- ing on to the next descriptor. This structure is also used to provide stimulus to another channel to indicate that it may continue. For example channel 1 may be configured to transfer a header into a buffer while channel 2 is simultaneously transferring data into the same structure.
Page 993: Interaction With The Emu
Reference Manual LDMA - Linked DMA Name Description This bit-field serves as the SYNCTRIG match value. A sync match triggers the load of the next linked DMA structure as specified by link_mode, when: (SYNCTRIG & MATCHEN) == (MATCHVAL & MATCHEN). 25.3.7.3 WRI Descriptor Structure This descriptor defines a write-immediate structure.
Page 994: Interrupts
Reference Manual LDMA - Linked DMA 25.3.9 Interrupts The LDMA_IF Interrupt flag register contains one DONE bit for each channel and one combined ERROR bit. When enabled, these in- terrupts are available as interrupts to the M33 core. They are combined into one interrupt vector, DMA_INT. If the interrupt for the DMA is enabled in the ARM M33 core, an interrupt will be made if one or more of the interrupt flags in LDMA_IF and their corresponding bits in LDMA_IEN are set.
Page 995: Descriptor Linked List
Reference Manual LDMA - Linked DMA 25.4.2 Descriptor Linked List This example shows how to use a Linked List of descriptors. Each descriptor has a link address which points to the next descriptor in the list. A descriptor may be removed from the Linked list by altering the Link address of the one before it to point to the one after it. Descriptor Linked lists are useful when handling an array of buffers for communication data.
Page 996 Reference Manual LDMA - Linked DMA To start execution of the linked list of descriptors: • Write the absolute address of the first descriptor to the LINKADR field of the LDMA_CH0_LINK register • Set the LINK bit of LDMA_CH0_LINK register. •...
Page 997 Reference Manual LDMA - Linked DMA 25.4.3 Single Descriptor Looped Transfer This example demonstrates how to use looping using a single descriptor. This method allows a single DMA transfer to be repeated a specified number of times. The looping descriptor is stored in memory and reloaded by hardware. After a specified number of iterations, the transfer stops.
Page 998: Descriptor List With Looping
Reference Manual LDMA - Linked DMA 25.4.4 Descriptor List with Looping This example uses a descriptor list in memory with looping over multiple descriptors. This example also uses the looping feature and continues on with the next sequential descriptor after looping completes. The descriptor list in memory is shown in figure Figure 25.7 Descriptor List with Looping on page 998.
Page 999: Simple Inter-Channel Synchronization
Reference Manual LDMA - Linked DMA 25.4.5 Simple Inter-Channel Synchronization The LDMA controller features synchronization structures which allow differing channels and/or hardware events to pause a DMA se- quence, and wait for a synchronizing event to restart it. In this example DMA channel 0 and 1 are tasked with the transfer of different sets of data. Channel 0 has two transfer structures, and channel 1 just one, but channel 0 must wait until channel 1 has completed its transfer before it starts its second transfer structure.
Page 1000 Reference Manual LDMA - Linked DMA SYNC[7] STRUCTTYPE=-SYNC STRUCTTYPE=XFER wait SYNCTRIG[7]=1 STRUCTTYPE=XFER C not fetched until sync_trig[7] is set STRUCTTYPE=SYNC STRUCTTYPE=XFER set SYNC[7] Time Figure 25.8. Simple Intra-channel Synchronization Example Both A and Y effectively start at the same time. A finishes earlier, then it links to B, which waits for the SYNCTRIG[7] bit to be set before loading C.

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