Texas Instruments MSP430FR59 Series Manuals

Manuals and User Guides for Texas Instruments MSP430FR59 Series. We have 1 Texas Instruments MSP430FR59 Series manual available for free PDF download: User Manual

Texas Instruments MSP430FR59 Series User Manual

Texas Instruments MSP430FR59 Series User Manual (1024 pages)

Brand: Texas Instruments | Category: Motherboard | Size: 6 MB

Table of Contents

List of Figures

19
- Table of Contents
  19
- BOR, POR, and PUC Reset Circuit
  49
- Interrupt Priority
  50
- Interrupt Processing
  52
- Interrupt Sources, Flags, and Vectors
  53
- Return from Interrupt
  53
- Operation Modes
  57
- Operation Modes
  58
- Requested Vs Actual LPM
  58
- Connection of Unused Pins
  62
- Devices Descriptor Table
  66
- Tag Values
  67
- REF Calibration Tags
  68
- ADC Calibration Tags
  69
- BSL Configuration Tags
  70
- Random Number Tags
  70
- BSL_CIF_CONFIG Values
  71
- 1.15 SFR Registers
  72
- SFRIE1 Register
  73
- SFRIE1 Register Description
  73
- SFRIFG1 Register
  74
- SFRIFG1 Register Description
  74
- SFRRPCR Register
  75
- SFRRPCR Register Description
  75
- 1.16 SYS Registers
  76
- SYSCTL Register
  77
- SYSCTL Register Description
  77
- SYSJMBC Register
  78
- SYSJMBC Register Description
  78
- SYSJMBI0 Register
  79
- SYSJMBI0 Register Description
  79
- SYSJMBI1 Register
  79
- SYSJMBI1 Register Description
  79
- SYSJMBO0 Register
  80
- SYSJMBO0 Register Description
  80
- SYSJMBO1 Register
  80
- SYSJMBO1 Register Description
  80
- SYSSNIV Register
  81
- SYSSNIV Register Description
  81
- SYSUNIV Register
  81
- SYSUNIV Register Description
  81
- SYSRSTIV Register
  82
- SYSRSTIV Register Description
  82
- PMM Block Diagram
  84
- Voltage Failure and Resulting PMM Actions
  85
- PMM Action at Device Power-Up
  86
- PMM Registers
  88
- PMMCTL0 Register
  89
- PMMCTL0 Register Description
  89
- PMMCTL1 Register
  90
- PMMCTL1 Register Description
  90
- PMMIFG Register
  91
- PMMIFG Register Description
  91
- PM5CTL0 Register
  92
- PM5CTL0 Register Description
  92
- Clock System Block Diagram
  95
- HFFREQ Settings
  97
- Module Request Clock System
  99
- System Clocks, Power Modes, and Clock Requests
  100
- Oscillator Fault Logic
  101
- Switch MCLK from DCOCLK to LFXTCLK
  102
- MEMORYMAP Registers
  103
- CTL0 Register
  104
- CTL0 Register Field Descriptions
  104
- CTL1 Register
  105
- CTL1 Register Field Descriptions
  105
- CTL2 Register
  106
- CTL2 Register Field Descriptions
  106
- CTL3 Register
  107
- CTL3 Register Field Descriptions
  107
- CTL4 Register
  108
- CTL4 Register Field Descriptions
  108
- CTL5 Register
  110
- CTL5 Register Field Descriptions
  110
- CTL6 Register
  111
- CTL6 Register Field Descriptions
  111
- MSP430X CPU Block Diagram
  114
- PC Storage on the Stack for Interrupts
  115
- PC Storage on the Stack for CALLA
  116
- Program Counter
  116
- PUSH SP, POP SP Sequence
  117
- PUSHX.A Format on the Stack
  117
- Stack Pointer
  117
- Stack Usage
  117
- SR Bit Description
  118
- SR Bits
  118
- Values of Constant Generators CG1, CG2
  119
- Register-Byte and Byte-Register Operation
  120
- Register-Word Operation
  120
- Register - Address-Word Operation
  121
- Word-Register Operation
  121
- Address-Word - Register Operation
  122
- Source and Destination Addressing
  122
- Indexed Mode in Lower 64KB
  124
- Indexed Mode in Upper Memory
  125
- Overflow and Underflow for Indexed Mode
  126
- Example for Indexed Mode
  127
- Symbolic Mode Running in Lower 64KB
  130
- Symbolic Mode Running in Upper Memory
  131
- Overflow and Underflow for Symbolic Mode
  132
- MSP430 Double-Operand Instruction Format
  141
- MSP430 Double-Operand Instructions
  142
- MSP430 Single-Operand Instructions
  142
- Conditional Jump Instructions
  143
- Emulated Instructions
  143
- Format of Conditional Jump Instructions
  143
- Interrupt, Return, and Reset Cycles and Length
  144
- MSP430 Format II Instruction Cycles and Length
  144
- MSP430 Format I Instructions Cycles and Length
  145
- Description of the Extension Word Bits for Register Mode
  146
- Extension Word for Non-Register Modes
  146
- Extension Word for Register Modes
  146
- Description of Extension Word Bits for Non-Register Modes
  147
- Example for Extended Register or Register Instruction
  147
- Example for Extended Immediate or Indexed Instruction
  148
- Extended Double-Operand Instructions
  148
- Extended Format I Instruction Formats
  149
- Extended Format II Instruction Format
  150
- Extended Single-Operand Instructions
  150
- BRA Instruction Format
  151
- CALLA Instruction Format
  151
- PUSHM and POPM Instruction Format
  151
- RRCM, RRAM, RRUM, and RLAM Instruction Format
  151
- Extended Emulated Instructions
  152
- Address Instructions, Operate on 20-Bit Register Data
  153
- MSP430X Format II Instruction Cycles and Length
  154
- MSP430X Format I Instruction Cycles and Length
  155
- Address Instruction Cycles and Length
  156
- Instruction Map of MSP430X
  157
- Decrement Overlap
  177
- Stack after a RET Instruction
  196
- Destination Operand-Arithmetic Shift Left
  198
- Destination Operand-Carry Left Shift
  199
- Rotate Right Arithmetically RRA.B and RRA.W
  200
- Rotate Right through Carry RRC.B and RRC.W
  201
- Swap Bytes in a Register
  208
- Swap Bytes in Memory
  208
- Rotate Left Arithmetically-RLAM[.W] and RLAM.A
  235
- Destination Operand-Arithmetic Shift Left
  236
- Destination Operand-Carry Left Shift
  237
- Rotate Right Arithmetically RRAM[.W] and RRAM.A
  238
- Rotate Right Arithmetically RRAX(.B,.A) - Non-Register Mode
  240
- Rotate Right Arithmetically RRAX(.B,.A) - Register Mode
  240
- Rotate Right through Carry RRCM[.W] and RRCM.A
  242
- Rotate Right through Carry RRCX(.B,.A) - Non-Register Mode
  244
- Rotate Right through Carry RRCX(.B,.A) - Register Mode
  244
- Rotate Right Unsigned RRUM[.W] and RRUM.A
  245
- Rotate Right Unsigned RRUX(.B,.A) - Register Mode
  246
- Swap Bytes SWPBX.A in Memory
  250
- Swap Bytes SWPBX.A Register Mode
  250
- Swap Bytes SWPBX[.W] in Memory
  251
- Swap Bytes SWPBX[.W] Register Mode
  251
- Sign Extend SXTX.A
  252
- Sign Extend SXTX[.W]
  252
- MPY32 Block Diagram
  272
- Result Availability (MPYFRAC = 0, MPYSAT = 0)
  273
- OP1 Registers
  274
- OP2 Registers
  274
  - Mode
    275
- SUMEXT and MPYC Contents
  275
- Q14 Format Representation
  277
- Q15 Format Representation
  277
- Result Availability in Fractional Mode (MPYFRAC = 1, MPYSAT = 0)
  278
- Result Availability in Saturation Mode (MPYSAT = 1)
  279
- Saturation Flow Chart
  279
- Multiplication Flow Chart
  281
- MPY32 Registers
  285
- Alternative Registers
  286
- MPY32CTL0 Register
  287
- MPY32CTL0 Register Description
  287
- FRAM Controller Overview
  288
Fram Controller (Frctl)

289
- Chapter 7
  290
- FRAM Controller Block Diagram
  290
- FRAM Introduction
  290
- FRAM Organization
  290
- FRCTL Module Operation
  290
- Programming FRAM Devices
  291
- Wait State Control
  291
- Fram Ecc
  292
- FRAM Power Control
  292
- FRAM Write Back
  292
- FRAM Power Control Diagram
  293
  - FRAM Cache
    293
- 7.10 FRCTL Registers
  294
- FRCTL0 Register
  295
- FRCTL0 Register Description
  295
  - FRCTL Registers
    295
- GCCTL0 Register
  296
- GCCTL0 Register Description
  296
- GCCTL1 Register
  297
- GCCTL1 Register Description
  297
Fram Controller a (Frctl_A)

298
- Chapter 8
  299
- FRAM Controller a (FRCTL_A) Introduction
  299
  - FRAM Controller a (FRCTL_A) Operation
    299
- FRCTL_A Block Diagram
  299
- FRAM Memory Access Speed
  301
- FRAM Power Mode Transition
  302
  - Fram Ecc
    302
    
    FRAM Power Control
    302
- FRAM Power Control Diagram
  303
  - FRAM Cache
    303
- FRCTL0 Register
  305
- FRCTL0 Register Field Descriptions
  305
  - FRCTL_A Registers
    306
  - FRAM Controller a (FRCTL_A)
    306
- GCCTL0 Register
  307
- GCCTL0 Register Field Descriptions
  307
- GCCTL1 Register
  309
- GCCTL1 Register Field Descriptions
  309
Memory Protection Unit (Mpu)

311
- Chapter 9
  312
- Memory Protection Unit (MPU) Introduction
  312
- Memory Protection Unit Overview
  312
- Address Comparator Bit Selection
  313
  - MPU Segments
    313
- Example of Segment Border Register Fixed Bits When FRAM Size = 128KB
  313
- Example of Segment Border Register Fixed Bits When FRAM Size = 256KB
  313
- Segment Border Register
  313
- Segmentation of Main Memory
  314
- IP Encapsulation Access Rights
  315
- IP Encapsulation Access Rights Equivalent Schematic
  315
- MPU Border Selection Example 64KB (004000H to 013Fffh)
  316
- Segment Access Rights
  317
  - MPU Access Management Settings
    317
- Access Rights to IVT
  318
  - MPU Violations
    318
  - MPU Lock
    318
  - How to Enable MPU and IPE Segments
    318
- IPE Signatures
  319
- Ipe_Init_Structure
  320
- MPU Registers
  321
- MPUCTL0 Register
  322
- MPUCTL0 Register Description
  322
- MPUCTL1 Register
  323
- MPUCTL1 Register Description
  323
- MPUSEGB2 Register
  324
- MPUSEGB2 Register Description
  324
- MPUSEGB1 Register
  325
- MPUSEGB1 Register Description
  325
- MPUSAM Register
  326
- MPUSAM Register Description
  327
- MPUIPC0 Register
  328
- MPUIPC0 Register Description
  328
- MPUIPSEGB2 Register
  329
- MPUIPSEGB1 Register
  330
- RAM Power Mode Transitions into and out of LPM3 or LPM4
  332
- 10.3 RAMCTL Registers
  334
- CTL0 Register
  335
- CTL0 Register Field Descriptions
  335
- CTL1 Register
  337
- CTL1 Register Field Descriptions
  337
- DMA Controller Block Diagram
  340
- DMA Addressing Modes
  341
- DMA Transfer Modes
  342
- DMA Single Transfer State Diagram
  343
- DMA Block Transfer State Diagram
  345
- DMA Burst-Block Transfer State Diagram
  347
- DMA Trigger Operation
  349
- Maximum Single-Transfer DMA Cycle Time
  350
- 11.3 DMA Registers
  353
- DMACTL0 Register
  355
- DMACTL0 Register Description
  355
- DMACTL1 Register
  356
- DMACTL1 Register Description
  356
- DMACTL2 Register
  357
- DMACTL2 Register Description
  357
- DMACTL3 Register
  358
- DMACTL3 Register Description
  358
- DMACTL4 Register
  359
- DMACTL4 Register Description
  359
- Dmaxctl Register
  360
- Dmaxctl Register Description
  360
- Dmaxsa Register
  362
- Dmaxsa Register Description
  362
- Dmaxda Register
  363
- Dmaxda Register Description
  363
- Dmaxsz Register
  364
- Dmaxsz Register Description
  364
- DMAIV Register
  365
- DMAIV Register Description
  365
- I/O Configuration
  366
- I/O Function Selection
  369
- 12.4 Digital I/O Registers
  374
- Pxiv Register
  388
- Pxiv Register Description
  388
- P1DIR Register Description
  389
- Pxdir Register
  389
- Pxin Register
  389
- Pxin Register Description
  389
- Pxout Register
  389
- Pxout Register Description
  389
- Pxren Register
  390
- Pxren Register Description
  390
- Pxsel0 Register
  390
- Pxsel0 Register Description
  390
- Pxsel1 Register
  390
- Pxsel1 Register Description
  390
- Pxie Register
  391
- Pxie Register Description
  391
- Pxies Register
  391
- Pxies Register Description
  391
- Pxselc Register
  391
- Pxselc Register Description
  391
- Pxifg Register
  392
- Pxifg Register Description
  392
- Capacitive Touch I/O Principle
  394
- Capacitive Touch I/O Block Diagram
  395
- Captouch Registers
  396
- Captioxctl Register
  397
- Captioxctl Register Description
  397
- AES Accelerator Block Diagram
  399
- AES Operation Modes Overview
  400
- AES State Array Input and Output
  400
- AES Encryption Process for 128-Bit Key
  403
- AES Decryption Process Using Aesopx = 01 for 128-Bit Key
  404
- AES Decryption Process Using Aesopx = 10 and 11 for 128-Bit Key
  405
- AES Trigger 0-2' Operation When AESCMEN
  407
- AES and DMA Configuration for ECB Encryption
  408
- ECB Encryption
  408
- AES DMA Configuration for ECB Decryption
  409
- ECB Decryption
  409
- AES and DMA Configuration for CBC Encryption
  410
- CBC Encryption
  410
- AES and DMA Configuration for CBC Decryption
  411
- CBC Decryption
  411
- AES and DMA Configuration for OFB Encryption
  413
- OFB Encryption
  413
- AES and DMA Configuration for OFB Decryption
  414
- OFB Decryption
  414
- AES and DMA Configuration for CFB Encryption
  415
- CFB Encryption
  415
- AES and DMA Configuration for CFB Decryption
  416
- CFB Decryption
  416
- AES256 Registers
  417
- AESACTL0 Register
  418
- AESACTL0 Register Description
  418
- AESACTL1 Register
  420
- AESACTL1 Register Description
  420
- AESASTAT Register
  421
- AESASTAT Register Description
  421
- AESAKEY Register
  422
- AESAKEY Register Description
  422
- AESADIN Register
  423
- AESADIN Register Description
  423
- AESADOUT Register
  424
- AESADOUT Register Description
  424
- AESAXDIN Register
  425
- AESAXDIN Register Description
  425
- AESAXIN Register
  426
- AESAXIN Register Description
  426
- LFSR Implementation of CRC-CCITT Standard, Bit 0 Is the MSB of the Result
  428
- Implementation of CRC-CCITT Using the CRCDI and CRCINIRES Registers
  430
- CRC Registers
  432
- CRCDI Register
  433
- CRCDI Register Description
  433
- CRCDIRB Register
  433
- CRCDIRB Register Description
  433
- CRCINIRES Register
  434
- CRCINIRES Register Description
  434
- CRCRESR Register
  434
- CRCRESR Register Description
  434
- LFSR Implementation of CRC-CCITT as Defined in Standard (Bit 0 Is MSB)
  436
- LFSR Implementation of CRC32-ISO3309 as Defined in Standard (Bit 0 Is MSB)
  436
- CRC32 Registers
  439
- CRC32DIW0 Register
  440
- CRC32DIW0 Register Description
  440
- CRC32DIW1 Register
  440
- CRC32DIW1 Register Description
  440
- CRC32DIRBW0 Register
  441
- CRC32DIRBW0 Register Description
  441
- CRC32DIRBW1 Register
  441
- CRC32DIRBW1 Register Description
  441
- CRC32INIRESW0 Register
  442
- CRC32INIRESW0 Register Description
  442
- CRC32INIRESW1 Register
  442
- CRC32INIRESW1 Register Description
  442
- CRC32RESRW0 Register
  443
- CRC32RESRW0 Register Description
  443
- CRC32RESRW1 Register
  443
- CRC32RESRW1 Register Description
  443
- CRC16DIL0 Register Description
  444
- CRC16DIRBW0 Register
  444
- CRC16DIW0 Register
  444
- CRC16INIRESW0 Register
  445
- CRC16INIRESW0 Register Description
  445
- CRC16RESRW0 Register
  445
- CRC16RESRW0 Register Description
  445
- LEA System Block Diagram
  447
- LEA Command Groups
  448
- DSP Library and Mspware Versions for the LEA
  449
- USS and USS_A Block Diagram
  452
- USS and USS_A Submodule Connections
  453
- Auto Mode and Register Mode
  454
- Time Mark Events
  454
- USS_PWRREQ Signal Source
  455
- Control Signals Among USS Submodules
  456
- USS/USS_A Block Diagram
  459
- UUPS Block Diagram
  460
- USS Power State
  461
- USS Power State Control Flow
  462
- USS Power States and State Changes
  462
- Device Power Modes and USS Power States
  463
- Internal Control Signals
  463
- USS Power Control
  463
- ASQ Trigger
  464
- Power States after Measurement Completion
  465
- 19.7 UUPS Registers
  467
- UUPSIIDX Register
  468
- UUPSIIDX Register Field Descriptions
  468
- UUPSMIS Register
  469
- UUPSMIS Register Field Descriptions
  469
- UUPSRIS Register
  470
- UUPSRIS Register Field Descriptions
  470
- UUPSIMSC Register
  471
- UUPSIMSC Register Field Descriptions
  471
- UUPSICR Register
  472
- UUPSICR Register Field Descriptions
  472
- UUPSISR Register
  473
- UUPSISR Register Field Descriptions
  473
- UUPSDESCLO Register
  474
- UUPSDESCHI Register
  475
- UUPSDESCHI Register Field Descriptions
  475
- UUPSCTL Register
  476
- UUPSCTL Register Field Descriptions
  476
- HSPLL Block Diagram
  479
- USS or USS_A Block Diagram
  479
- HSPLL Registers
  483
- HSPLLIIDX Register
  484
- HSPLLIIDX Register Field Descriptions
  484
- HSPLLMIS Register
  485
- HSPLLMIS Register Field Descriptions
  485
- HSPLLRIS Register
  486
- HSPLLRIS Register Field Descriptions
  486
- HSPLLIMSC Register
  487
- HSPLLIMSC Register Field Descriptions
  487
- HSPLLICR Register
  488
- HSPLLICR Register Field Descriptions
  488
- HSPLLISR Register
  489
- HSPLLISR Register Field Descriptions
  489
- HSPLLDESCLO Register
  490
- HSPLLDESCHI Register
  491
- HSPLLDESCHI Register Field Descriptions
  491
- HSPLLCTL Register
  492
- HSPLLCTL Register Field Descriptions
  492
- HSPLLUSSXTLCTL Register
  494
- PPG or PPG_A Block Diagram
  497
- USS or USS_A Block Diagram
  497
- PPG or PPG_A Internal State Diagrams for Single Tone
  498
- PPG_A State Diagram for Dual Tone
  500
- PPG_A State Diagram for Trill Tone
  501
- PPG_A Software Flow Chart for Multi Tone
  502
- PHY Output Pins
  504
- Trim Registers
  505
- SAPH or SAPH_A Analog Input Signal Chain
  506
- Before Excitation
  507
- Supply to the Rx Multiplexer
  507
- Before Reception
  509
- ASQ Block Diagram
  511
- Time Mark Events
  512
- Auto Mode and Register Mode
  513
- Auto Mode and Register Mode Example
  514
- Ultra-Low-Power Bias Mode Example
  515
- SAPH Registers
  516
- SAPHIIDX/SAPH_AIIDX Register
  518
- SAPHMIS/SAPH_AMIS Register
  519
- SAPHRIS/SAPH_ARIS Register
  520
- SAPHIMSC/SAPH_AIMSC Register
  521
- SAPHIMSC/SAPH_AIMSC Register Field Descriptions
  521
- SAPHICR/SAPH_AICR Register
  522
- SAPHISR/SAPH_AISR Register
  523
- SAPHDESCLO/SAPH_ADESCLO Register
  524
- SAPHDESCLO/SAPH_ADESCLO Register Field Descriptions
  524
- SAPHDESCHI/SAPH_ADESCHI Register
  525
- SAPHDESCHI/SAPH_ADESCHI Register Field Descriptions
  525
- SAPHKEY/SAPH_AKEY Register
  526
- SAPHKEY/SAPH_AKEY Register Field Descriptions
  526
- SAPHOCTL0/SAPH_AOCTL0 Register
  527
- SAPHOCTL0/SAPH_AOCTL0 Register Field Descriptions
  527
- SAPHOCTL1/SAPH_AOCTL1 Register
  528
- SAPHOCTL1/SAPH_AOCTL1 Register Field Descriptions
  528
- SAPHOSEL/SAPH_AOSEL Register
  529
- SAPHOSEL/SAPH_AOSEL Register Field Descriptions
  529
- SAPHCH0PUT/SAPH_ACH0PUT Register
  530
- SAPHCH0PUT/SAPH_ACH0PUT Register Field Descriptions
  530
- SAPHCH0PDT/SAPH_ACH0PDT Register
  531
- SAPHCH0PDT/SAPH_ACH0PDT Register Field Descriptions
  531
- SAPHCH0TT/SAPH_ACH0TT Register
  532
- SAPHCH0TT/SAPH_ACH0TT Register Field Descriptions
  532
- SAPHCH1PUT/SAPH_ACH1PUT Register
  533
- SAPHCH1PUT/SAPH_ACH1PUT Register Field Descriptions
  533
- SAPHCH1PDT/SAPH_ACH1PDT Register
  534
- SAPHCH1PDT/SAPH_ACH1PDT Register Field Descriptions
  534
- SAPHCH1TT/SAPH_ACH1TT Register
  535
- SAPHCH1TT/SAPH_ACH1TT Register Field Descriptions
  535
- SAPHMCNF/SAPH_AMCNF Register
  536
- SAPHMCNF/SAPH_AMCNF Register Field Descriptions
  536
- SAPHTACTL/SAPH_ATACTL Register
  537
- SAPHTACTL/SAPH_ATACTL Register Field Descriptions
  537
- SAPHICTL0/SAPH_AICTL0 Register
  538
- SAPHICTL0/SAPH_AICTL0 Register Field Descriptions
  538
- SAPHBCTL/SAPH_ABCTL Register
  540
- SAPHBCTL/SAPH_ABCTL Register Field Descriptions
  540
- SAPHPGC/SAPH_APGC Register
  542
- SAPHPGLPER/SAPH_APGLPER Register
  543
- SAPHPGLPER/SAPH_APGLPER Register Field Descriptions
  543
- SAPHPGHPER/SAPH_APGHPER Register
  544
- SAPHPGHPER/SAPH_APGHPER Register Field Descriptions
  544
- SAPHPGCTL/SAPH_APGCTL Register
  545
- SAPHPGCTL/SAPH_APGCTL Register Field Descriptions
  545
- SAPHPPGTRIG/SAPH_APPGTRIG Register
  547
- SAPHPPGTRIG/SAPH_APPGTRIG Register Field Descriptions
  547
- SAPH_AXPGCTL Register
  548
- SAPH_AXPGLPER Register
  549
- SAPH_AXPGHPER Register
  550
- SAPHASCTL0/SAPH_AASCTL0 Register
  551
- SAPHASCTL0/SAPH_AASCTL0 Register Field Descriptions
  551
- SAPHASCTL1/SAPH_AASCTL1 Register
  553
- SAPHASCTL1/SAPH_AASCTL1 Register Field Descriptions
  553
- SAPHASQTRIG/SAPH_AASQTRIG Register
  555
- SAPHASQTRIG/SAPH_AASQTRIG Register Field Descriptions
  555
- SAPHAPOL/SAPH_AAPOL Register
  556
- SAPHAPOL/SAPH_AAPOL Register Field Descriptions
  556
- SAPHAPLEV/SAPH_AAPLEV Register
  557
- SAPHAPLEV/SAPH_AAPLEV Register Field Descriptions
  557
- SAPHAPHIZ/SAPH_AAPHIZ Register
  558
- SAPHAPHIZ/SAPH_AAPHIZ Register Field Descriptions
  558
- SAPHATM_A/SAPH_AATM_A Register
  559
- SAPHATM_A/SAPH_AATM_A Register Field Descriptions
  559
- SAPHATM_B/SAPH_AATM_B Register
  560
- SAPHATM_B/SAPH_AATM_B Register Field Descriptions
  560
- SAPHATM_C/SAPH_AATM_C Register
  561
- SAPHATM_C/SAPH_AATM_C Register Field Descriptions
  561
21.8.40 Saphatm_D/Saph_Aatm_D Register (Offset = 74H) [Reset = 0H]

562
- SAPHATM_D/SAPH_AATM_D Register
  562
- SAPHATM_D/SAPH_AATM_D Register Field Descriptions
  562
- SAPHATM_E/SAPH_AATM_E Register
  563
- SAPHATM_E/SAPH_AATM_E Register Field Descriptions
  563
- SAPHATM_F/SAPH_AATM_F Register
  564
- SAPHTBCTL/SAPH_ATBCTL Register
  565
- SAPHTBCTL/SAPH_ATBCTL Register Field Descriptions
  565
- SAPHATIMLO/SAPH_AATIMLO Register
  566
- SAPHATIMLO/SAPH_AATIMLO Register Field Descriptions
  566
- SAPHATIMHI /SAPH_AATIMHI Register Field Descriptions
  567
- SAPHATIMHI/SAPH_AATIMHI Register
  567
- USS Block Diagram
  569
- SDHS Block Diagram
  570
- Sigma-Delta Principle
  571
- Filter Structure
  572
- SDHS Filter Frequency Response, SDHSCTL1.OSR
  572
- Digital Filter Block Diagram
  573
- SDHS Filter Frequency Response Within F
  573
- SDHS Filter Frequency Response Within F
  574
- SDHS Filter Frequency Response, SDHSCTL1.OSR
  574
- SDHS Filter Frequency Response Within F
  575
- Sdhsctl1.Osr
  575
- Data Format
  576
- SDHS Filter Frequency Response Within F
  576
- Sdhsctl1.Osr
  576
- Bits Selection from Filter to the Data Register (SDHSCTL0.DALGN = 0)
  577
- SDHSDT Register
  577
- Bits Selection from Filter to the Data Register (SDHSCTL0.DALGN = 1)
  578
- Data Output Path
  580
- PGA Gain Table
  580
- Control Signals for Power and Conversion
  582
- SDHS Power and Conversion Trigger Source
  582
- USS Auto Mode and Register Mode
  582
- SDHS Operation in Register Mode (SDHSCTL0.TRGSRC = 0)
  583
- SDHS Operation as Part of USS Measurement (SDHSCTL0.TRGSRC = 1)
  584
- Example Using SDHSCTL3.TRIGEN Bit (SDHSCTL0.AUTOSSDIS = 0)
  586
- Example Using SDSCTL3.TRIGEN Bit (SDHSCTL0.AUTOSSDIS = 1)
  587
- Conversion Control Mode
  588
- Conversion Start and Stop When SDHSCTL0.AUTOSSDIS
  588
- Conversion Start and Stop When SDHSCTL0.AUTOSSDIS
  589
- First Interrupt Position with SDHSCTL0.INTDLY
  589
- Conversion Control Mode
  590
- SDHSCTL0.AUTOSSDIS = 0, SDHSCTL2.SMPCTLOFF = 0, SDHSCTL0.INTDLY = 0, Total Sample
  590
- SDHSCTL0.AUTOSSDIS = 1, SDHSCTL2.SMPCTLOFF = 0, SDHSCTL0.INTDLY = 0, Total Sample
  591
- SDHSCTL0.AUTOSSDIS = 1, SDHSCTL2.SMPCTLOFF = 0, SDHSCTL0.INTDLY = M, Total Sample
  591
- SDHS Conversion Stop Conditions
  592
- SDHS Response to Conversion Stop Signals When Data Conversion Is Not Running
  593
- 22.5 SDHS Registers
  595
- SDHSIIDX Register
  596
- SDHSIIDX Register Field Descriptions
  596
- SDHSMIS Register
  597
- SDHSMIS Register Field Descriptions
  597
- SDHSRIS Register
  598
- SDHSRIS Register Field Descriptions
  598
- SDHSIMSC Register
  600
- SDHSIMSC Register Field Descriptions
  600
- SDHSICR Register
  601
- SDHSICR Register Field Descriptions
  601
- SDHSISR Register
  602
- SDHSISR Register Field Descriptions
  602
- SDHSDESCLO Register
  603
- SDHSDESCHI Register
  604
- SDHSCTL0 Register
  605
- SDHSCTL0 Register Field Descriptions
  605
- SDHSCTL1 Register
  607
- SDHSCTL1 Register Field Descriptions
  607
- SDHSCTL2 Register
  608
- SDHSCTL2 Register Field Descriptions
  608
- SDHSCTL3 Register
  609
- SDHSCTL3 Register Field Descriptions
  609
- SDHSCTL4 Register
  610
- SDHSCTL4 Register Field Descriptions
  610
- SDHSCTL5 Register
  611
- SDHSCTL5 Register Field Descriptions
  611
- SDHSCTL6 Register
  613
- SDHSCTL6 Register Field Descriptions
  613
- SDHSCTL7 Register
  614
- SDHSCTL7 Register Field Descriptions
  614
- SDHSDT Register Field Descriptions
  615
- SDHSWINHITH Register
  616
- SDHSWINLOTH Register
  617
- SDHSDTCDA Register
  618
- MTIF Use Case
  620
- MTIF Internal Interfaces
  621
  - Bitfield "PGPW
    621
    
    Interface (SAPH, SAPH_A)
    621
- MTIF Pulse Diagram
  621
- MTIF Initialization
  622
- PGFS Values
  622
- Setting the Pulse Rate
  622
- Reading the Pulse Rate
  623
- Figure
  624
- MTIF Block Diagram
  624
- 23.4 MTIF Registers
  625
- MTIFPGCNF Register
  626
- MTIFPGCNF Register Field Descriptions
  626
  - R/W-0H
    626
- MTIFPGKVAL Register
  627
  - Type Reset Description R/W
    627
    
    Reset Type: PUC
    627
- MTIFPGCTL Register
  628
- MTIFPGCTL Register Field Descriptions
  628
- MTIFPGSR Register
  629
- MTIFPGSR Register Field Descriptions
  629
- MTIFPCCNF Register
  630
- MTIFPCCNF Register Field Descriptions
  630
- MTIFPCR Register
  631
- MTIFPCR Register Field Descriptions
  631
- MTIFPCCTL Register
  632
- MTIFPCCTL Register Field Descriptions
  632
- MTIFPCSR Register
  633
- MTIFPCSR Register Field Descriptions
  633
- MTIFTPCTL Register
  634
- MTIFTPCTL Register Field Descriptions
  634
- SLAU367P - October 2012 - Revised April 2020
  635
- Submit Documentation Feedback
  635
- Watchdog Timer Block Diagram
  637
- WDTCTL Register
  641
- WDTCTL Register Description
  641
- Timer_A Registers
  642
- Timer_A Block Diagram
  644
- Timer Modes
  646
- Up Mode
  646
- Up Mode Flag Setting
  646
- Continuous Mode
  647
- Continuous Mode Flag Setting
  647
- Continuous Mode Time Intervals
  647
- Up/Down Mode
  648
- Up/Down Mode Flag Setting
  648
- Output Unit in Up/Down Mode
  649
- Capture Cycle
  650
- Capture Signal (SCS = 1)
  650
- Output Modes
  651
- Output Example - Timer in up Mode
  652
- Output Example - Timer in Continuous Mode
  653
- Output Example - Timer in Up/Down Mode
  654
- Taxctl Register
  658
- Taxctl Register Description
  658
- Taxr Register
  659
- Taxr Register Description
  659
- Taxcctln Register
  660
- Taxcctln Register Description
  660
- Capture/Compare Interrupt Flag
  661
- Taxccrn Register
  662
- Taxccrn Register Description
  662
- Taxiv Register
  662
- Taxiv Register Description
  662
- Taxex0 Register
  663
- Taxex0 Register Description
  663
- Timer_B Registers
  664
- Timer_B Block Diagram
  666
- Timer Modes
  668
- Up Mode
  668
- Up Mode Flag Setting
  668
- Continuous Mode
  669
- Continuous Mode Flag Setting
  669
- Continuous Mode Time Intervals
  669
- Up/Down Mode
  670
- Up/Down Mode Flag Setting
  670
- Output Unit in Up/Down Mode
  671
- Capture Cycle
  672
- Capture Signal (SCS = 1)
  672
- Tbxcln Load Events
  673
- Compare Latch Operating Modes
  674
- Output Modes
  674
- Output Example - Timer in up Mode
  675
- Output Example - Timer in Continuous Mode
  676
- Output Example - Timer in Up/Down Mode
  677
- Capture/Compare Tbxccr0 Interrupt Flag
  678
- Tbxctl Register
  681
- Tbxctl Register Description
  681
- Tbxr Register
  683
- Tbxr Register Description
  683
- Tbxcctln Register
  684
- Tbxcctln Register Description
  684
- Tbxccrn Register
  686
- Tbxccrn Register Description
  686
- Tbxiv Register
  687
- Tbxiv Register Description
  687
- Tbxex0 Register
  688
- Tbxex0 Register Description
  688
- 27.1 RTC Overview
  689
- RTC_B Registers
  690
- RTC_B Block Diagram
  692
- RTCCTL0 Register
  700
- RTCCTL0 Register Description
  700
- RTCCTL1 Register
  701
- RTCCTL1 Register Description
  701
- RTCCTL2 Register
  702
- RTCCTL2 Register Description
  702
- RTCCTL3 Register
  702
- RTCCTL3 Register Description
  702
- RTCSEC Register
  703
- RTCSEC Register Description
  703
- RTCMIN Register
  704
- RTCMIN Register Description
  704
- RTCHOUR Register
  705
- RTCHOUR Register Description
  705
- RTCDAY Register
  706
- RTCDAY Register Description
  706
- RTCDOW Register
  706
- RTCDOW Register Description
  706
- RTCMON Register
  707
- RTCMON Register Description
  707
- RTCYEAR Register
  708
- RTCYEAR Register Description
  708
- RTCAMIN Register
  709
- RTCAMIN Register Description
  709
- RTCAHOUR Register
  710
- RTCAHOUR Register Description
  710
- RTCADOW Register
  711
- RTCADOW Register Description
  711
- RTCADAY Register
  712
- RTCADAY Register Description
  712
- RTCPS0CTL Register Description
  713
- RTCPS1CTL Register Description
  714
- RTCPS0 Register
  715
- RTCPS0 Register Description
  715
- RTCPS1 Register
  715
- RTCPS1 Register Description
  715
- RTCIV Register
  716
- RTCIV Register Description
  716
- BCD2BIN Register
  717
- BCD2BIN Register Description
  717
- BIN2BCD Register
  717
- BIN2BCD Register Description
  717
- RTC_C Block Diagram (RTCMODE = 1)
  720
- RTC_C Offset Error Calibration and Temperature Compensation Scheme
  727
- RTC_C Functional Block Diagram in Counter Mode (RTCMODE = 0)
  729
- Rtccapx Pin Configuration
  733
- RTC_C Registers
  735
- RTC_C Event and Tamper Detection Registers
  736
- RTC_C Real-Time Clock Counter Mode Aliases
  736
- RTCCTL0_L Register
  737
- RTCCTL0_H Register
  738
- RTCCTL1 Register
  739
- RTCCTL1 Register Description
  739
- RTCCTL3 Register
  740
- RTCCTL3 Register Description
  740
- RTCOCAL Register
  740
- RTCOCAL Register Description
  740
- RTCTCMP Register
  741
- RTCTCMP Register Description
  741
- RTCNT1 Register
  742
- RTCNT1 Register Description
  742
- RTCNT2 Register
  742
- RTCNT2 Register Description
  742
- RTCNT3 Register
  742
- RTCNT3 Register Description
  742
- RTCNT4 Register
  742
- RTCNT4 Register Description
  742
- RTCSEC Register
  743
- RTCSEC Register Description
  743
- RTCMIN Register
  744
- RTCMIN Register Description
  744
- RTCHOUR Register
  745
- RTCHOUR Register Description
  745
- RTCDAY Register
  746
- RTCDAY Register Description
  746
- RTCDOW Register
  746
- RTCDOW Register Description
  746
- RTCMON Register
  747
- RTCMON Register Description
  747
- RTCYEAR Register
  748
- RTCYEAR Register Description
  748
- RTCAMIN Register
  749
- RTCAMIN Register Description
  749
- RTCAHOUR Register
  750
- RTCAHOUR Register Description
  750
- RTCADOW Register
  751
- RTCADOW Register Description
  751
- RTCADAY Register
  752
- RTCADAY Register Description
  752
- RTCPS0CTL Register
  753
- RTCPS0CTL Register Description
  753
- RTCPS1CTL Register
  754
- RTCPS1CTL Register Description
  754
- RTCPS0 Register
  756
- RTCPS0 Register Description
  756
- RTCPS1 Register
  756
- RTCPS1 Register Description
  756
- RTCIV Register
  757
- RTCIV Register Description
  757
- BCD2BIN Register
  758
- BCD2BIN Register Description
  758
- BIN2BCD Register
  758
- BIN2BCD Register Description
  758
- Rtcsecbakx Register
  759
- Rtcsecbakx Register Description
  759
- Rtcminbakx Register
  760
- Rtcminbakx Register Description
  760
- Rtchourbakx Register
  761
- Rtchourbakx Register Description
  761
- Rtcdaybakx Register
  762
- Rtcdaybakx Register Description
  762
- Rtcmonbakx Register
  763
- Rtcmonbakx Register Description
  763
- Rtcyearbakx Register
  764
- Rtcyearbakx Register Description
  764
- RTCTCCTL0 Register
  765
- RTCTCCTL1 Register
  765
- Rtccapxctl Register
  766
- Rtccapxctl Register Description
  766
- Eusci_Ax Block Diagram - UART Mode (UCSYNC = 0)
  769
- Character Format
  770
- Idle-Line Format
  771
- Address-Bit Multiprocessor Format
  772
- Auto Baud-Rate Detection - Break/Synch Sequence
  773
- Auto Baud-Rate Detection - Synch Field
  773
- UART Vs Irda Data Format
  774
- Receive Error Conditions
  775
- Glitch Suppression, Eusci_A Receive Not Started
  776
- BITCLK Baud-Rate Timing with UCOS16
  777
- Modulation Pattern Examples
  777
- BITCLK16 Modulation Pattern
  778
- BRCLK /Baud Rate
  779
- Receive Error
  781
- Recommended Settings for Typical Crystals and Baud Rates
  782
- UART State Change Interrupt Flags
  784
- 30.4 Eusci_A UART Registers
  786
- Ucaxctlw0 Register
  787
- Ucaxctlw0 Register Description
  787
- Ucaxctlw0 Register Description
  788
- Ucaxctlw1 Register
  788
- Ucaxctlw1 Register Description
  788
- Ucaxbrw Register
  789
- Ucaxbrw Register Description
  789
- Ucaxmctlw Register
  789
- Ucaxmctlw Register Description
  789
- Ucaxstatw Register
  790
- Ucaxstatw Register Description
  790
- Ucaxrxbuf Register
  791
- Ucaxrxbuf Register Description
  791
- Ucaxtxbuf Register
  791
- Ucaxtxbuf Register Description
  791
- Ucaxabctl Register
  792
- Ucaxabctl Register Description
  792
- Ucaxirctl Register
  793
- Ucaxirctl Register Description
  793
- Ucaxie Register
  794
- Ucaxie Register Description
  794
- Ucaxifg Register
  795
- Ucaxifg Register Description
  795
- Ucaxiv Register
  796
- Ucaxiv Register Description
  796
- Eusci Block Diagram - SPI Mode
  799
- Ucxste Operation
  800
- Eusci Master and External Slave (UCSTEM = 0)
  801
- Eusci Slave and External Master
  802
- Eusci SPI Timing with UCMSB
  804
- 31.4 Eusci_A SPI Registers
  806
- Ucaxctlw0 Register
  807
- Ucaxbrw Register
  808
- Ucaxbrw Register Description
  808
- Ucaxstatw Register
  809
- Ucaxstatw Register Description
  809
- Ucaxrxbuf Register
  810
- Ucaxrxbuf Register Description
  810
- Ucaxtxbuf Register
  811
- Ucaxtxbuf Register Description
  811
- Ucaxie Register
  812
- Ucaxie Register Description
  812
- Ucaxifg Register
  813
- Ucaxifg Register Description
  813
- Ucaxiv Register
  814
- Ucaxiv Register Description
  814
- 31.5 Eusci_B SPI Registers
  815
- Ucbxctlw0 Register
  816
- Ucbxctlw0 Register Description
  816
- Ucbxbrw Register
  817
- Ucbxbrw Register Description
  817
- Ucbxstatw Register Description
  817
- Ucbxrxbuf Register Description
  818
- Ucbxtxbuf Register
  818
- Ucbxie Register
  819
- Ucbxie Register Description
  819
- Ucbxifg Register
  819
- Ucbxifg Register Description
  819
- Ucbxiv Register
  820
- Ucbxiv Register Description
  820
- Eusci_B Block Diagram - I
  823
  - Bus Connection Diagram
    824
  - Module Data Transfer
    825
- Bit Transfer on I C Bus
  825
  - Module 7-Bit Addressing Format
    825
- I2C Master 10-Bit Addressing Mode
  825
  - Module 10-Bit Addressing Format
    826
- C Module Addressing Format with Repeated START Condition
  826
  - Time-Line Legend
    828
  - Slave Transmitter Mode
    828
- C Slave Receiver Mode
  829
- C Slave 10-Bit Addressing Mode
  830
- C Master Transmitter Mode
  832
- I 2 C Master Receiver Mode
  834
- Arbitration Procedure between Two Master Transmitters
  836
- Clock Generators During Arbitration
  837
- Glitch Filter Length Selection Bits
  837
- Synchronization of Two I
  837
- C State Change Interrupt Flags
  842
- Ucbxctlw0 Register
  845
- Ucbxctlw0 Register Description
  845
- Ucbxctlw1 Register
  847
- Ucbxctlw1 Register Description
  847
- Ucbxbrw Register
  849
- Ucbxbrw Register Description
  849
- Ucbxstatw Register
  849
- Ucbxtbcnt Register
  850
- Ucbxrxbuf Register
  851
- Ucbxrxbuf Register Description
  851
- Ucbxtxbuf Register
  851
- Ucbxtxbuf Register Description
  851
- Ucbxi2Coa0 Register
  852
- Ucbxi2Coa1 Register
  853
- Ucbxi2Coa2 Register
  853
- Ucbxaddrx Register
  854
- Ucbxi2Coa3 Register
  854
- Ucbxaddmask Register
  855
- Ucbxi2Csa Register
  855
- Ucbxi2Csa Register Description
  855
- Ucbxie Register
  856
- Ucbxie Register Description
  856
- Ucbxifg Register
  858
- Ucbxifg Register Description
  858
- Ucbxiv Register
  860
- Ucbxiv Register Description
  860
- REF_A Block Diagram
  862
- REFCTL0 Register
  866
- REFCTL0 Register Description
  866
- ADC12_B Block Diagram
  870
- Analog Multiplexer T-Switch
  872
- Extended Sample Mode with Internal Reference in 12-Bit Mode
  874
- Extended Sample Mode Without Internal Reference in 12-Bit Mode
  874
- Analog Input Equivalent Circuit
  875
- Pulse Sample Mode First Conversion or Where ADC12MSC = 0 in 12-Bit Mode
  875
- Pulse Sample Mode Subsequent Conversions in 12-Bit Mode
  875
- ADC12_B Conversion Result Formats
  876
- Conversion Mode Summary
  877
- Single-Channel Single-Conversion Mode, ADC12ISSH
  878
- Sequence-Of-Channels Mode, ADC12ISSH
  879
- Repeat-Single-Channel Mode, ADC12ISSH
  880
- Repeat-Sequence-Of-Channels Mode, ADC12ISSH
  881
- Typical Temperature Sensor Transfer Function
  883
- ADC12_B Grounding and Noise Considerations
  884
- 34.3 ADC12_B Registers
  887
- ADC12CTL0 Register
  893
- ADC12CTL0 Register Description
  894
- ADC12CTL1 Register
  895
- ADC12CTL1 Register Description
  896
- ADC12CTL2 Register
  897
- ADC12CTL2 Register Description
  897
- ADC12CTL3 Register
  898
- Adc12Memx Register
  899
- Adc12Memx Register Description
  899
- Adc12Mctlx Register
  900
- Adc12Mctlx Register Description
  901
- ADC12HI Register
  902
- ADC12HI Register Description
  902
- ADC12LO Register
  902
- ADC12LO Register Description
  902
- ADC12IER0 Register
  903
- ADC12IER0 Register Description
  903
- ADC12IER1 Register
  905
- ADC12IER1 Register Description
  905
- ADC12IER2 Register
  907
- ADC12IER2 Register Description
  907
- ADC12IFGR0 Register
  908
- ADC12IFGR0 Register Description
  909
- ADC12IFGR1 Register
  910
- ADC12IFGR1 Register Description
  911
- ADC12IFGR2 Register
  912
- ADC12IV Register
  913
- ADC12IV Register Description
  913
- Comparator_E Block Diagram
  916
- Comparator_E Sample-And-Hold
  918
- RC-Filter Response at the Output of the Comparator
  919
- Reference Generator Block Diagram
  919
- Transfer Characteristic and Power Dissipation in a CMOS Inverter and Buffer
  920
- Temperature Measurement System
  921
- Timing for Temperature Measurement Systems
  921
- CECTL0 Register
  924
- CECTL0 Register Description
  924
- CECTL1 Register
  925
- CECTL1 Register Description
  925
- CECTL2 Register
  926
- CECTL2 Register Description
  926
- CECTL3 Register
  927
- CECTL3 Register Description
  927
- CEINT Register
  929
- CEINT Register Description
  929
- CEIV Register
  930
- CEIV Register Description
  930
- Differences between LCD_B and LCD_C
  932
- LCD Controller Block Diagram
  933
- LCD Memory for Static and 2-Mux to 4-Mux Mode - Example for 160 Segments
  934
- LCD Memory for 5-Mux to 8-Mux Mode - Example for 160 Segments
  935
- Bias Generation
  938
- Bias Voltages and External Pins
  939
- LCD Voltage and Biasing Characteristics
  940
- Example Static Waveforms
  943
- Example 2-Mux Waveforms
  944
- Example 3-Mux Waveforms
  945
- Example 4-Mux Waveforms
  946
- Example 6-Mux Waveforms
  947
- Example 8-Mux, 1/3 Bias Waveforms (LCDLP = 0)
  948
- Example 8-Mux, 1/3 Bias Low-Power Waveforms (LCDLP = 1)
  949
- LCD_C Control Registers
  950
- LCD_C Memory Registers for Static and 2-Mux to 4-Mux Modes
  951
- LCD Blinking Memory Registers for Static and 2-Mux to 4-Mux Modes
  952
- LCD Memory Registers for 5-Mux to 8-Mux
  953
- LCDCCTL0 Register
  955
- LCDCCTL0 Register Description
  955
- LCDCCTL1 Register
  957
- LCDCCTL1 Register Description
  957
- LCDCBLKCTL Register
  958
- LCDCMEMCTL Register
  959
- LCDCMEMCTL Register Description
  959
- LCDCVCTL Register
  960
- LCDCVCTL Register Description
  960
- LCDCPCTL0 Register
  962
- LCDCPCTL1 Register
  962
- LCDCPCTL2 Register
  963
- LCDCPCTL3 Register
  963
- LCDCCPCTL Register
  964
- LCDCCPCTL Register Description
  964
- LCDCIV Register
  964
- LCDCIV Register Description
  964
- ESI Block Diagram
  966
- ESI Analog Front End AFE1 Block Diagram
  968
- ESI Analog Front End AFE2 Block Diagram
  969
- Excitation and Sample-And-Hold Circuitry
  970
- Analog Input Equivalent Circuit
  971
- ESICAX and ESISH Input Selection
  971
- Analog Front-End Output Timing
  972
- Selected Output Bits
  972
- Analog Hysteresis with DAC Registers
  973
- Selected DAC Registers
  973
- DAC Register Select When TESTDX=1
  974
- Timing State Machine Block Diagram
  975
- TSM State Duration
  977
- Test Cycle Insertion
  978
- TSM Example Register Values
  978
- Timing State Machine Example
  979
- Pre-Processing Unit
  980
- Timer_A Output Stage of the Analog Front End
  980
- ESI Processing State Machine Block Diagram
  981
- Simplest PSM State Diagram (ESIV2SEL=1)
  984
- 37.2.7 ESI Interrupts
  985
- LC Sensor Oscillations
  986
- Sensor Connections for the Oscillation Test
  987
- LC Sensor Connections for the Envelope Test
  988
- LC Sensor Connections for the Envelope Test
  989
- Resistive Sensor Connections
  990
- Quadrature Decoding State Diagram
  991
- Sensor Position and Quadrature Signals (S1=PPUS1, S2=PPUS2)
  991
- Quadrature Decoding PSM Table
  992
- 37.3 ESI Registers
  993
- ESIDEBUG1 Register
  994
- ESIDEBUG2 Register
  994
- ESIDEBUG3 Register
  994
- ESIDEBUG4 Register
  995
- ESIDEBUG4 Register Description
  995
- ESIDEBUG5 Register
  995
- ESIDEBUG5 Register Description
  995
- ESICNT0 Register
  996
- ESICNT0 Register Description
  996
- ESICNT1 Register
  996
- ESICNT1 Register Description
  996
- ESICNT2 Register
  997
- ESICNT2 Register Description
  997
- ESICNT3 Register
  997
- ESICNT3 Register Description
  997
- ESIIV Register
  998
- ESIIV Register Description
  998
- ESIINT1 Register
  999
- ESIINT1 Register Description
  999
- ESIINT2 Register
  1001
- ESIINT2 Register Description
  1001
- ESIAFE Register
  1003
- ESIAFE Register Description
  1003
- ESIPPU Register
  1005
- ESIPPU Register Description
  1005
- ESITSM Register
  1006
- ESITSM Register Description
  1006
- TSM Start Trigger ACLK Divider
  1007
- ESIPSM Register
  1008
- ESIPSM Register Description
  1008
- ESIOSC Register
  1009
- ESIOSC Register Description
  1009
- ESICTL Register
  1010
- ESICTL Register Description
  1010
- ESITHR1 Register
  1012
- ESITHR1 Register Description
  1012
- ESITHR2 Register
  1012
- ESITHR2 Register Description
  1012
- Esidac1Rx Register
  1013
- Esidac1Rx Register Description
  1013
- Esidac2Rx Register
  1013
- Esidac2Rx Register Description
  1013
- Esitsmx Register
  1014
- Esitsmx Register Description
  1014
- Extended Scan Interface Processing State Machine Table Entry Description
  1016
- Extended Scan Interface Processing State Machine Table Entry Register
  1016
- Large Implementation of EEM
  1019
- EEM Configurations
  1022
- WDT_A Registers
  1023

Advertisement

Advertisement

Related Products

Texas Instruments Categories

Motherboard Control Unit Microcontrollers Computer Hardware Calculator

More Texas Instruments Manuals