Cypress CYW9P62S1-43012EVB-01 Manual page 12

Figure 2-2 shows the block diagram of the CYW9-BASE-01 Pioneer Board (modified for
CYW9P62S1-43012EVB-01).
Figure 2-3 shows the block diagram of the CYW9P62S1-43012CAR-01 Carrier Module.
Figure 2-2. Block Diagram of Pioneer Board
P5LP_VDD
USB
(Micro‐B)
VTARG
Monitoring
Figure 2-3. Block Diagram of CYW9P62S1-43012CAR-01 Carrier Module
Carrier
Module
Footprint
CYW9P62S1-43012EVB-01 PSoC 62S1 Wi-Fi BT Pioneer Kit Guide, Doc. # 002-28722 Rev. *B
CYW9‐BASE‐01 Architecture Block Diagram
KitProg3 Mode 10‐pin SWD/
Switch & LED JTAG Header
1.8~3.3V
SWD
VTARG_REF 1.8~3.3V
JTAG
VTARG_REF
SWD
I2C/UART_RX/UART_TX
P5LP_VDD
Level
Translator
KitProg3
(PSoC 5LP)
P5LP_VDD
Level
Translator
2 x CapSense Buttons,
PSoC 6 MCU GPIOs (39 I/Os)
XRES
USB
SDIO (6 I/Os)
BT UART (4 I/Os)
Control (3 I/Os)
WL UART (2 I/Os)
BT I2S (4 I/Os)
VDDA (1.8V)
VDDD (1.8V – 3.3V)
VDDIO0 (1.8V)
VDDIO1 (1.8V)
VDD_NS (1.8V – 3.3V)
VBACKUP (1.8V – 3.3V)
VDDUSB (3.3V)
VBAT (3.2V – 4.2V)
VDDIO_WL (1.8V)
20‐pin ETM Reset
Header
Button
SWD
JTAG
TRACE
VTARG
UART_RTS
UART_CTS
VDDIO0
VDDIO_WL
BT_UART TX, RX, CTS, RTS
Carrier
WL_UART TX, RX, KP_GPIO_0
Module
I2C EEPROM
3.3V, VTARG
KP_VBUS
1 x 5‐segment
CapSense Slider
USB Device
USI SiP
Module
Kit Operation
Cypress Device
VDDA
Potentiometer
No Load
VBACKUP
Loaded Device
1 x User Button
User LEDs
(Red, Orange)
QSPI NOR
Flash
QSPI F‐RAM
VDDIO0
microSD Card
VDDIO0
Slot
PSoC 6 MCU
I/O Headers
(Arduino)
I/O Headers
(Non Arduino)
UMC
Connector
RF Switch
RF
Matching
UMC
Network
Connector
CINTA, CINTB
CMOD
Crystals
32.768 KHz &
17.2032 MHz
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