Kit Operation; Board Details - Cypress CYW9P62S1-43012EVB-01 Manual

2.

Kit Operation

This chapter introduces you to various features of the PSoC 62S1 Wi-Fi BT Pioneer Board, including
the theory of operation and the onboard KitProg3 programming and debugging functionality,
USB-UART and USB-I2C bridges.
2.1

Board Details

The PSoC 62S1 Wi-Fi BT Pioneer Board is built around a PSoC 6 MCU.
diagram of the PSoC 6 MCU device used on the board. For details of device features, see the
datasheet.
Figure 2-1. PSoC 6 MCU Block Diagram
PSoC 62
System Resources
Power
Sleep Control
POR BOD
OVP LVD
REF
PWRSYS-LP/ULP
Buck
Clock
Clock Control
ILO WDT
IMO ECO
FLL
1xPLL
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
Backup
Backup Control
BREG
RTC
WCO
Power Modes
Active/Sleep
LowePowerActive/Sleep
DeepSleep
Hibernate
Backup
CYW9P62S1-43012EVB-01 PSoC 62S1 Wi-Fi BT Pioneer Kit Guide, Doc. # 002-28722 Rev. *B
CPU Subsystem
SWJ/ETM/ITM/CTI
Cortex M4
FLASH SRAM
150 MHz (1.1V)
1024+32 KB 9x 32 KB
50 MHz (0.9V)
FPU, NVIC, MPU, BB
FLASH Controller SRAM Controller
8KB Cache
PCLK
Programmable Programmable
Analog
SAR ADC DAC
(12-bit) (12-bit)
UDB
x1 x1
SARMUX CTB/CTBm
2x OpAmp x1
IO Subsystem
SWJ/MTB/CTI
Cortex M0+
ROM
100 MHz (1.1V)
128 KB
25 MHz (0.9V)
MUL, NVIC, MPU
ROM Controller
8KB Cache
System Interconnect (Multi Layer AHB, MPU/SMPU, IPC)
Peripheral Interconnect (MMIO, PPU)
Digital
... UDB
x12
Port Interface & Digital System Interconnect (DSI)
High Speed I/O Matrix, Smart I/O, Boundary Scan
104 GPIOs (6 of these are OVT Pins)
Figure 2-1 shows the block
CRYPTO
DataWire/
DES/TDES,
DMA
AES,SHA,CRC,
2x 16 Ch TRNG,RSA/ECC
Accelerator
Initiator/MMIO Initiator/MMIO
Audio
Subsystem
device
DMA
MMIO
11