Zynq Apsoc Architecture - Digilent Cora Z7 Reference Manual

7/30/2019
Supply Circuits
5.0V Onboard Regulators, Arduino/chipKit Shield Connector, RGB
LEDs
3.3V FPGA I/O, USB port, Ethernet
1.0V FPGA, Ethernet
1.8V FPGA Auxiliary, USB port, Ethernet
1.35V FPGA, DDR3L memory
1.8V FPGA XADC
Table 1.1. Cora Z7 Power Rails.
1)
With JP3 set to "USB"

2 Zynq APSoC Architecture

The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS) and the Programmable Logic (PL). Figure 2.1 shows
an overview of the Zynq APSoC architecture, with the PS colored light green and the PL in yellow. Note that the PCIe Gen2 controller and
Multi-gigabit transceivers are not available on the Zynq-7010 or Zynq-7007S devices.
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Cora Z7 Reference Manual [Reference.Digilentinc]
Device
IC4: ON Semiconductor
NCP380
IC15: Dialog Semiconductor
DA9062
IC15: Dialog Semiconductor
DA9062
IC15: Dialog Semiconductor
DA9062
IC15: Dialog Semiconductor
DA9062
IC15: Dialog Semiconductor
DA9062
1)
Maximum
Current
2A
2.5A
1.5A
2.5A
100mA